SLVS237E August   1999  – March 2024 TPS766

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (Legacy Chip)
    5. 5.5 Thermal Information (New Chip)
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Characteristics: Supported ESR Range
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Power-Good Function
      6. 6.3.6 Output Pulldown
      7. 6.3.7 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Adjustable Device Feedback Resistors
        2. 7.2.2.2 Recommended Capacitor Types
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20230821-SS0I-FM4S-ZQ8J-HTDZBMP0CQTL-low.svg Figure 4-1 D Package,8-Pin SOIC(Top View)
Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
EN 4 I Enable pin. Driving the enable pin low enables the device. Driving this pin high disables the device. Low and high thresholds are listed in the Electrical Characteristics table.
FB/NC 1 I Adjustable version: Feedback pin. Input to the control-loop error amplifier. This pin sets the output voltage of the device by using external resistors. Do not float this pin.

Fixed version: Not internally connected. Leave this pin open or tied to ground for improved thermal performance.

GND 3 Ground pin.
IN 5, 6 I Input pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions. Place the input capacitor as close to the IN and GND pins of the device as possible.
OUT 7, 8 O Output pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions. Place the output capacitor as close to the OUT and GND pins of the device as possible.
PG 2 O Power-good output. Available in the open-drain output. A pullup resistor is required for the open-drain output type. If the power-good functionality is not used, ground this pin or leave floating. See the Power-Good Function section for more information.