SLVSDW6C April   2017  – April 2021 TPS7H1101A-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Power Good (PG)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable/Disable
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Stability
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Adjustable Output Voltage (Feedback Circuit)
        2. 8.2.1.2 PCL
        3. 8.2.1.3 High-Side Current Sense
        4. 8.2.1.4 Current Foldback
        5. 8.2.1.5 Transient Response
        6. 8.2.1.6 Current Sharing
        7. 8.2.1.7 Compensation
        8. 8.2.1.8 Output Noise
        9. 8.2.1.9 Capacitors
      2. 8.2.2 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.7 Compensation

Figure 8-13 shows a generic block diagram for TPS7H1101A-SP LDO with external compensation components. LDO incorporates nested loops, thus providing the high gain necessary to meet design performance.

GUID-C59635EE-5E11-4D58-B8E1-3CBF575F8535-low.gifFigure 8-13 TPS7H1101A-SP Compensation

Resistor divider composed of Rtop and Rbottom determine the output voltage set points as indicated by Equation 2.

Output capacitor COUT introduces a pole and a zero as shown in the following.

Equation 6. GUID-0921B652-B481-4BA6-A147-6347AB15A5A8-low.gif
Equation 7. GUID-AC9D7D61-9D51-4F4A-AE6E-B73E4F4581F9-low.gif

The TPS7H1101A-SP was designed so that the ESR of the output capacitor will not have a strong influence on the response of the LDO. However, an optional capacitor, Cx, can be added in parallel with the bottom feedback resistor to introduce a pole to cancel Fz_co. Equation 8 shows how to calculate the location of the pole introduced by Cx. To cancel the zero directly, Fp should be equal to Fz_co.

Equation 8. GUID-79C55ABE-012A-40FF-BE01-9B63B46ED806-low.gif

Cx is calculated to be 1000 pF for Co = 220 µF, Cesr = 45 mΩ, and Rbottom = 10 kΩ.

Figure 8-13 also includes a place holder for a feed forward capacitance Cff. Use of feed forward compensation can be more advantageous than use of Cx. Please reference application note Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator for additional information on usage of CFF.

Internal compensation in the LDO cancels the output capacitor pole introduced by COUT and RL.

Ccomp introduces a dominant pole at low frequency. TI recommends that a Ccomp value of 10 nF.