SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 Configurable Power Good

The power good indicator pin, PG, is an open drain pin that is asserted when the output voltage reaches the desired value. The PG pin may either be pulled-up through a resistor to VOUT, VIN, or another voltage level less than the recommended maximum of 7 V. Select the resistor size to keep the maximum current sunk by PG to under the recommended operating condition current maximum of 2 mA.

Note that if PG is pulled-up to an external voltage before either VIN or VBIAS are supplied to the device, PG may not be pulled-down due to insufficient drive strength. VIN(MIN_PG) is specified in the Electrical Characteristics table as the minimum value either VIN or VBIAS must reach for PG to have sufficient pull-down strength to pull-down PG to under 0.5 V at less than or equal to 0.6 mA. Once VIN and VBIAS reach their proper final voltages, the PG pin has full drive strength.

By feeding the output voltage through a resistor divider to the FB_PG pin, the PG assertion level can be configured. The FB_PG pin has a typical threshold of 300 mV. When this threshold is reached or exceeded, the PG pin is asserted. Equation 7 shows how to calculate the VOUT value where PG is asserted (it does not take into account the FB_PG pin leakage current which has minimal effect). As described in Section 8.3.5 the fast start circuitry will also turn-off when this level is reached.

Equation 7. VFB_PG(rising) = VOUT(assert_threshold) × RFBPG_BOT / (RFBPG_TOP + RFBPG_BOT)

To ensure PG is asserted by the time the final output voltage is reached, the worst case tolerances of output voltage, FB_PG threshold, and resistor tolerance levels must be taken into account. Generally, configuring the resistor divider so V(assert_threshold) is 90% or less than VOUT(final) is sufficient.

The PG deassert threshold can also be calculated using Equation 8.

Equation 8. VFB_PG(rising) - VFB_PG(hysteresis) = VOUT(deassert_threshold) × RFBPG_BOT / (RFBPG_TOP + RFBPG_BOT)

If the PG pin is not used, it may be pulled to ground. However, the FB_PG pin must still be properly configured if the fast start circuitry described in Section 8.3.5 is desired.