SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 Soft Start and Noise Reduction

In addition to setting the output voltage, the SS_SET pin serves two other important functions: programming the soft start time and creating a noise filter for the internal reference current. In most applications, at least a 4.7 μF capacitor is recommended in order to obtain sufficient low noise performance. Larger value capacitors may be acceptable; however, there are diminishing returns in reduced output noise in capacitor values larger than 4.7μF.

This capacitor also slows down the SS_SET voltage ramp rate, and therefore controls the LDO turn-on time (soft start). However, if the capacitor was only charged by the ISET current (nominally 100 μA), the startup time would be excessive. Therefore, there is an additional fast charge current source (IFS ≈ 2 mA) that is active during startup. Consequently, a 4.7μF capacitor will result in a nominal 3.7 ms soft start time. A simplified diagram of this circuitry is shown in Figure 8-3.

GUID-20201112-CA0I-NW6G-ZPPQ-KQNTHHXH0D6P-low.png Figure 8-3 Simplified Schematic Showing Startup Circuitry

This fast charge circuitry is active until the FB_PG threshold is reached (typically 300 mV). After the FB_PG threshold has been reached, the fast start current will turn off and the soft start time as shown in Equation 6 will be completed. CSS will continue charging to its final value (as determined by the RSET resistor) with the 100 μA (typ) reference current. An example startup waveform is shown in Figure 8-4. In this waveform it is assumed EN is fed a divided down version of VIN.

Equation 6. tSS ≈ CSS × VOUT(assert_threshold) / ISS_SET(startup)

where

  • tSS = soft start time
  • ISS_SET(startup) = IFS + ISET = 2.1 mA (typ)
  • V(assert_threshold) = configured value of VOUT for which PG is asserted (typically 90% of VOUT(final), see Section 8.3.6)

Note that the fast charge current (IFS) and set current (ISET) are both active during the soft start time (tSS) and are reported as ISS_SET(start) in the Electrical Characteristics table. This 2.1 mA typical value is valid for a 12 kΩ RREF resistor. As the fast charge current is internally derived from the current through the RREF resistor, values greater than or less than 12 kΩ will cause a decrease or increase of the IFS current respectively.

If the fast start circuitry is not desired, connect the FB_PG pin to VOUT. This will ensure the fast start circuitry is quickly turned-off as the FB_PG threshold is quickly reached. Note that this effects the PG pin behavior as well as described in Section 8.3.6.

GUID-20201112-CA0I-3TRK-N1H5-BBFDLVZZBGJ6-low.png Figure 8-4 Simplified Schematic Showing Startup Waveforms