SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.3 Output Voltage Accuracy

To determine the output voltage accuracy, the VACC specification with in the Section 6.5 table is consulted. VACC specifies a minimum accuracy of –1.3% and maximum accuracy of +1.2% across temperature. This specification applies across the complete temperature range of –55°C to 125°C, across all the input voltages (0.85 V ≤ VIN ≤ 7 V and 2.2 V ≤ VBIAS ≤ 14 V), and up to full load (1 mA ≤ IOUT ≤ 1.5 A). A few additional details to the measurement are noted in Section 8.3.2. The following sources of error are also added to calculate a system level accuracy:

  • Since post TID specifications are measured at room temperature (a MIL standard in order to avoid annealing at high temperatures), the TID drift is not part of the over temperature accuracy specification. The TPS7H1111 is specified post TID to have a minimum accuracy of –0.7% and maximum of +1.1%. This is compared to a pre-TID accuracy of –0.7% and maximum of +0.9%. Therefore, the specification increase due to TID is an additional 0.2% error being added. While the worst case TID drift of a single unit could be used instead, this may be excessively pessimistic as that would require a unit to have an initial room temperature accuracy near the maximum and a drift near the maximum values.
  • The external error due to the resistor tolerance of the RREF and RSET resistors need to be added. Since it is assumed the error is uncorrelated, it is decided to add the errors as a sum of squares. For the selected 0.1% tolerance RREF and RSET resistors, the total error is R(error) = sqrt(0.1%2+0.1%2) = +/– 0.14%.

Equation 15 is used to calculate the system error for output voltage accuracy.

Equation 15. System(error) = VACC + R(error) + TID(error)

Therefore, the negative error is System(error) = –1.3% – 0.14% – 0% = –1.44% and the positive error is System(error) = 1.2% + 0.14% + 0.2% = 1.54%. There the total system error due to the TPS7H1111 device, external resistors, and 100 krad(Si) of TID is +1.54%/–1.44%. If the total system error is centered, this comes to ±1.49%.

Lifetime drift data could similarly be added. Group C data may be used to aid this calculation. For this example, it is assumed the lifetime drift is minimal compared to the other sources of error and is therefore not added.