SLVSEN7D april   2019  – may 2023 TPS7H4001-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - All Devices
    6. 7.6  Electrical Characteristics: CDFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP (SHP) Option
    8. 7.8  Electrical Characteristics: HTSSOP (QMLP) Option
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Enable and Adjust UVLO
      7. 8.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 8.3.7.1 Internal Oscillator Mode
        2. 8.3.7.2 External Synchronization Mode
        3. 8.3.7.3 Primary-Secondary Operation Mode
      8. 8.3.8  Soft-Start (SS/TR)
      9. 8.3.9  Power Good (PWRGD)
      10. 8.3.10 Sequencing
      11. 8.3.11 Output Overvoltage Protection (OVP)
      12. 8.3.12 Overcurrent Protection
        1. 8.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Turn-On Behavior
      15. 8.3.15 Slope Compensation
        1. 8.3.15.1 Slope Compensation Requirements
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
          1. 9.2.2.7.1 Minimum Output Voltage
        8. 9.2.2.8 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDW|44
  • KGD|0
  • HKY|34
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision C (November 2022) to Revision D (May 2023)

  • Updated Features, Device Information, and Electrical Characteristics sections to include the HTSSOP (QMLP) package optionGo
  • Added QMLP orderable 5962R1820502PYE to Device Information table in Description sectionGo
  • Updated Device Information table in Description sectionGo
  • Added Device Options Table section to data sheetGo
  • Updated Voltage Reference section to include HTSSOP (SHP) optionGo

Changes from Revision B (September 2022) to Revision C (November 2022)

  • Changed SHP grade HTSSOP package option from Advanced Information to Production DataGo
  • Added EM die orderable TPS7H4001Y/EM to Device Information table in Description sectionGo
  • Updated footnote for Pin Functions table to specify CDFP package optionGo

Changes from Revision A (November 2020) to Revision B (September 2022)

  • Updated Features, Description, Device Information, Pin Configuration and Functions, Thermal Information, Electrical Characteristics, and Layout Guidelines sections to include the HTSSOP (SHP) package optionGo
  • Updated ESD CDM standard from JEDEC specification JESD22-C101 to ANSI/ESDA/JEDEC JS-002Go

Changes from Revision * (April 2020) to Revision A (November 2020)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Updated radiation performance in Features sectionGo
  • Updated Applications sectionGo
  • Updated Device Information table in Description sectionGo
  • Added bare die information to Pin Configuration and Functions sectionGo
  • Added additional thermal resistance parameters to Thermal Information tableGo
  • Updated specification for Junction-to-case (bottom) thermal resistance in Thermal Information table Go
  • Updated all minimum limits for Enable threshold in Electrical Characteristics tableGo
  • Updated 2.55 mV maximum limit for Error amplifier input offset voltage in Electrical Characteistics tableGo
  • Removed footnote in Electrical Characteristics table for Error amplifier transconductance, source and sink curents specificationsGo
  • Updated footnote in Electrical Characteristics table for COMP to Iswitch gm specification to "Bench verified. Not tested in production."Go
  • Updated all maximum limits for Internally set frequency in Electrical Characteristics tableGo
  • Updated all maximum limits for Externally set frequency for RT = 1.07 MΩ (1%) in Electrical Characteristics tableGo
  • Updated all limits for Externally set frequency for RT = 165 kΩ (1%) in Electrical Characteristics tableGo
  • Added Externally set frequency specification for RT = 73.2 kΩ (1%), VIN = 5 V, TID = 100 krad(Si) in Electrical Characteristics tableGo
  • Added footnote in Electrical Characteristics table for SYNC1/SYNC2 in low level threshold for PVIN = VIN = 7 VGo
  • Added footnote in Electrical Characteristics table for SYNC1/SYNC2 in high level threshold for PVIN = VIN = 7 V Go
  • Removed footnote in Electrical Characteristics table for SYNC1 in frequency range specification and added test conditionsGo
  • Updated 235 ns maximum limit for Minimum on time for VIN = 5 V in Electrical Characteristics tableGo
  • Added footnote to Electrical Characteristics table for SS/TR to VSENSE matchingGo
  • Added footnote in Electrical Characteristics table for High-side switch resistance with PVIN = VIN = 7 VGo
  • Added footnote in Electrical Characteristics table for Low-side switch resistance with PVIN = VIN = 7 VGo
  • Updated all typical and maximum limits for Low-side switch resistance for PVIN = VIN = 7 V, lead length = 3 mm in Electrical Characteristics tableGo
  • Updated footnote in Electrical Characteristics table for High-side switch current limit threshold and Low-side switch sourcing overcurrent threshold specifications to "Bench verified. Not tested in production."Go
  • Added footnote in Electrical Characteristics table for Low-side switch sinking overcurrent thresholdGo
  • Updated RT equation in Internal Oscillator Mode sectionGo
  • Changed title of Master-Slave Operation Mode section to Primary-Secondary Operation Mode Go
  • Updated input ripple current equation in Input Capacitor Selection sectionGo
  • Added Documentation Support to the Device and Documentation Support sectionGo