SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
STATUS3 register is a read-only register. Figure 7-27 shows STATUS3. Table 7-13 describes STATUS3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STANDALONE | V5AUV | CMWTO[1:0] | TW | PC | CH2STATUS | CH1STATUS | |
R-0b | RC-0b | RC-00b | RC-0b | RC-1b | RC-0b | RC-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | STANDALONE | R | 0 | Indicates standalone mode. This bit can be cleared by issuing the RESET or DETECT command (see RESET register). |
6 | V5AUV | RC | 0 | Indicates V5A undervoltage fault condition. |
5-4 | CMWTO | RC | 00 | Indicates the number of times the communication watchdog timer has expired. 00 = Default (normal operation) 01 = Watchdog has expired 1 time. 10 = Watchdog has expired 2 times. 11 = Watchdog has expired 3 times. Device transitions into limp-home mode. |
3 | TW | RC | 0 | Indicates overtemperature thermal warning |
2 | PC | RC | 1 | Power cycle bit is set at power up and is considered a fault. The PC bit must be cleared before the channels can be enabled. |
1 | CH2STATUS | RC | 0 | Logic OR of the fault bits for channel 2 excluding over temperature thermal warning. |
0 | CH1STATUS | RC | 0 | Logic OR of the fault bits for channel 1 excluding over temperature thermal warning. |