SLVSE03 Data sheet

SLVSE03B April 2019 – February 2021 TPS929120-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PWP|24
- MPDS372A

Thermal pad, mechanical data (Package|Pins)

PWP|24
- PPTD402

Orderable Information

7.6.1 FullMap Registers

Table 7-14 lists the FullMap registers. All register offset addresses not listed in Table 7-14 should be considered as reserved locations and the register contents should not be modified.

Table 7-14 FULLMAP Registers

Offset	Acronym	Register Name	Section
0h	IOUT0	Output Current Setting for CH0	Go
1h	IOUT1	Output Current Setting for CH1	Go
2h	IOUT2	Output Current Setting for CH2	Go
3h	IOUT3	Output Current Setting for CH3	Go
4h	IOUT4	Output Current Setting for CH4	Go
5h	IOUT5	Output Current Setting for CH5	Go
6h	IOUT6	Output Current Setting for CH6	Go
7h	IOUT7	Output Current Setting for CH7	Go
8h	IOUT8	Output Current Setting for CH8	Go
9h	IOUT9	Output Current Setting for CH9	Go
Ah	IOUT10	Output Current Setting for CH10	Go
Bh	IOUT11	Output Current Setting for CH11	Go
20h	PWM0	Output PWM Duty-cycle Setting for CH0	Go
21h	PWM1	Output PWM Duty-cycle Setting for CH1	Go
22h	PWM2	Output PWM Duty-cycle Setting for CH2	Go
23h	PWM3	Output PWM Duty-cycle Setting for CH3	Go
24h	PWM4	Output PWM Duty-cycle Setting for CH4	Go
25h	PWM5	Output PWM Duty-cycle Setting for CH5	Go
26h	PWM6	Output PWM Duty-cycle Setting for CH6	Go
27h	PWM7	Output PWM Duty-cycle Setting for CH7	Go
28h	PWM8	Output PWM Duty-cycle Setting for CH8	Go
29h	PWM9	Output PWM Duty-cycle Setting for CH9	Go
2Ah	PWM10	Output PWM Duty-cycle Setting for CH10	Go
2Bh	PWM11	Output PWM Duty-cycle Setting for CH11	Go
40h	PWML0	Output PWM Duty-cycle Setting Lower bits for CH0	Go
41h	PWML1	Output PWM Duty-cycle Setting Lower bits for CH1	Go
42h	PWML2	Output PWM Duty-cycle Setting Lower bits for CH2	Go
43h	PWML3	Output PWM Duty-cycle Setting Lower bits for CH3	Go
44h	PWML4	Output PWM Duty-cycle Setting Lower bits for CH4	Go
45h	PWML5	Output PWM Duty-cycle Setting Lower bits for CH5	Go
46h	PWML6	Output PWM Duty-cycle Setting Lower bits for CH6	Go
47h	PWML7	Output PWM Duty-cycle Setting Lower bits for CH7	Go
48h	PWML8	Output PWM Duty-cycle Setting Lower bits for CH8	Go
49h	PWML9	Output PWM Duty-cycle Setting Lower bits for CH9	Go
4Ah	PWML10	Output PWM Duty-cycle Setting Lower bits for CH10	Go
4Bh	PWML11	Output PWM Duty-cycle Setting Lower bits for CH11	Go
50h	CONF_EN0	Channel Enable Register 0	Go
51h	CONF_EN1	Channel Enable Register 1	Go
54h	CONF_DIAGEN0	Diagnostics Enable Register 0	Go
55h	CONF_DIAGEN1	Diagnostics Enable Register 1	Go
56h	CONF_MISC0	Miscellanous Register 0	Go
57h	CONF_MISC1	Miscellanous Register 1	Go
58h	CONF_MISC2	Miscellanous Register 2	Go
59h	CONF_MISC3	Miscellanous Register 3	Go
5Ah	CONF_MISC4	Miscellanous Register 4	Go
5Bh	CONF_MISC5	Miscellanous Register 5	Go
60h	CLR	Configuration Register for Clear	Go
61h	CONF_LOCK	Configuration Register for LOCK	Go
62h	CONF_MISC6	Miscellanous Register 6	Go
63h	CONF_MISC7	Miscellanous Register 7	Go
64h	CONF_MISC8	Miscellanous Register 8	Go
65h	CONF_MISC9	Miscellanous Register 9	Go
70h	FLAG0	Device status flag register 0	Go
71h	FLAG1	Device status flag register 1	Go
72h	FLAG2	Device status flag register 2	Go
73h	FLAG3	Device status flag register 3	Go
74h	FLAG4	Device status flag register 4	Go
75h	FLAG5	Device status flag register 5	Go
77h	FLAG7	Device status flag register 7	Go
78h	FLAG8	Device status flag register 8	Go
7Bh	FLAG11	Device status flag register 11	Go
7Ch	FLAG12	Device status flag register 12	Go
7Dh	FLAG13	Device status flag register 13	Go
7Eh	FLAG14	Device status flag register 14	Go
80h	EEPI0	EEPROM Output Current Setting for CH0	Go
81h	EEPI1	EEPROM Output Current Setting for CH1	Go
82h	EEPI2	EEPROM Output Current Setting for CH2	Go
83h	EEPI3	EEPROM Output Current Setting for CH3	Go
84h	EEPI4	EEPROM Output Current Setting for CH4	Go
85h	EEPI5	EEPROM Output Current Setting for CH5	Go
86h	EEPI6	EEPROM Output Current Setting for CH6	Go
87h	EEPI7	EEPROM Output Current Setting for CH7	Go
88h	EEPI8	EEPROM Output Current Setting for CH8	Go
89h	EEPI9	EEPROM Output Current Setting for CH9	Go
8Ah	EEPI10	EEPROM Output Current Setting for CH10	Go
8Bh	EEPI11	EEPROM Output Current Setting for CH11	Go
A0h	EEPP0	EEPROM Output PWM Duty-cycle Setting for CH0	Go
A1h	EEPP1	EEPROM Output PWM Duty-cycle Setting for CH1	Go
A2h	EEPP2	EEPROM Output PWM Duty-cycle Setting for CH2	Go
A3h	EEPP3	EEPROM Output PWM Duty-cycle Setting for CH3	Go
A4h	EEPP4	EEPROM Output PWM Duty-cycle Setting for CH4	Go
A5h	EEPP5	EEPROM Output PWM Duty-cycle Setting for CH5	Go
A6h	EEPP6	EEPROM Output PWM Duty-cycle Setting for CH6	Go
A7h	EEPP7	EEPROM Output PWM Duty-cycle Setting for CH7	Go
A8h	EEPP8	EEPROM Output PWM Duty-cycle Setting for CH8	Go
A9h	EEPP9	EEPROM Output PWM Duty-cycle Setting for CH9	Go
AAh	EEPP10	EEPROM Output PWM Duty-cycle Setting for CH10	Go
ABh	EEPP11	EEPROM Output PWM Duty-cycle Setting for CH11	Go
C0h	EEPM0	EEPROM Miscellaneous registers 0	Go
C1h	EEPM1	EEPROM Miscellaneous registers 1	Go
C2h	EEPM2	EEPROM Miscellaneous registers 2	Go
C3h	EEPM3	EEPROM Miscellaneous registers 3	Go
C4h	EEPM4	EEPROM Miscellaneous registers 4	Go
C5h	EEPM5	EEPROM Miscellaneous registers 5	Go
C6h	EEPM6	EEPROM Miscellaneous registers 6	Go
C7h	EEPM7	EEPROM Miscellaneous registers 7	Go
C8h	EEPM8	EEPROM Miscellaneous registers 8	Go
C9h	EEPM9	EEPROM Miscellaneous registers 9	Go
CAh	EEPM10	EEPROM Miscellaneous registers 10	Go
CBh	EEPM11	EEPROM Miscellaneous registers 11	Go
CFh	EEPM15	EEPROM CRC Check Value Registers	Go

Complex bit access types are encoded to fit into small table cells. Table 7-15 shows the codes that are used for access types in this section.

Table 7-15 FullMap Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.6.1.1 IOUT0 Register (Offset = 0h) [reset = X]

IOUT0 is shown in Figure 7-19 and described in Table 7-16.

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Figure 7-19 IOUT0 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT0
R-0h		R/W-X

Table 7-16 IOUT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT0	R/W	X	Output current setting for OUT0 Load EEPI0 data when reset

7.6.1.2 IOUT1 Register (Offset = 1h) [reset = X]

IOUT1 is shown in Figure 7-20 and described in Table 7-17.

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Figure 7-20 IOUT1 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT1
R-0h		R/W-X

Table 7-17 IOUT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT1	R/W	X	Output current setting for OUT1 Load EEPI1 data when reset

7.6.1.3 IOUT2 Register (Offset = 2h) [reset = X]

IOUT2 is shown in Figure 7-21 and described in Table 7-18.

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Figure 7-21 IOUT2 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT2
R-0h		R/W-X

Table 7-18 IOUT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT2	R/W	X	Output current setting for OUT2 Load EEPI2 data when reset

7.6.1.4 IOUT3 Register (Offset = 3h) [reset = X]

IOUT3 is shown in Figure 7-22 and described in Table 7-19.

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Figure 7-22 IOUT3 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT3
R-0h		R/W-X

Table 7-19 IOUT3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT3	R/W	X	Output current setting for OUT3 Load EEPI3 data when reset

7.6.1.5 IOUT4 Register (Offset = 4h) [reset = X]

IOUT4 is shown in Figure 7-23 and described in Table 7-20.

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Figure 7-23 IOUT4 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT4
R-0h		R/W-X

Table 7-20 IOUT4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT4	R/W	X	Output current setting for OUT4 Load EEPI4 data when reset

7.6.1.6 IOUT5 Register (Offset = 5h) [reset = X]

IOUT5 is shown in Figure 7-24 and described in Table 7-21.

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Figure 7-24 IOUT5 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT5
R-0h		R/W-X

Table 7-21 IOUT5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT5	R/W	X	Output current setting for OUT5 Load EEPI5 data when reset

7.6.1.7 IOUT6 Register (Offset = 6h) [reset = X]

IOUT6 is shown in Figure 7-25 and described in Table 7-22.

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Figure 7-25 IOUT6 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT6
R-0h		R/W-X

Table 7-22 IOUT6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT6	R/W	X	Output current setting for OUT6 Load EEPI6 data when reset

7.6.1.8 IOUT7 Register (Offset = 7h) [reset = X]

IOUT7 is shown in Figure 7-26 and described in Table 7-23.

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Figure 7-26 IOUT7 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT7
R-0h		R/W-X

Table 7-23 IOUT7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT7	R/W	X	Output current setting for OUT7 Load EEPI7 data when reset

7.6.1.9 IOUT8 Register (Offset = 8h) [reset = X]

IOUT8 is shown in Figure 7-27 and described in Table 7-24.

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Figure 7-27 IOUT8 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT8
R-0h		R/W-X

Table 7-24 IOUT8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT8	R/W	X	Output current setting for OUT8 Load EEPI8 data when reset

7.6.1.10 IOUT9 Register (Offset = 9h) [reset = X]

IOUT9 is shown in Figure 7-28 and described in Table 7-25.

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Figure 7-28 IOUT9 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT9
R-0h		R/W-X

Table 7-25 IOUT9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT9	R/W	X	Output current setting for OUT9 Load EEPI9 data when reset

7.6.1.11 IOUT10 Register (Offset = Ah) [reset = X]

IOUT10 is shown in Figure 7-29 and described in Table 7-26.

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Figure 7-29 IOUT10 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT10
R-0h		R/W-X

Table 7-26 IOUT10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT10	R/W	X	Output current setting for OUT10 Load EEPI10 data when reset

7.6.1.12 IOUT11 Register (Offset = Bh) [reset = X]

IOUT11 is shown in Figure 7-30 and described in Table 7-27.

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Figure 7-30 IOUT11 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_IOUT11
R-0h		R/W-X

Table 7-27 IOUT11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	CONF_IOUT11	R/W	X	Output current setting for OUT11 Load EEPI11 data when reset

7.6.1.13 PWM0 Register (Offset = 20h) [reset = X]

PWM0 is shown in Figure 7-31 and described in Table 7-28.

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Figure 7-31 PWM0 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT0
R/W-X

Table 7-28 PWM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT0	R/W	X	PWM Dutycycle Register Setting for CH0 Load EEPP0 data when reset

7.6.1.14 PWM1 Register (Offset = 21h) [reset = X]

PWM1 is shown in Figure 7-32 and described in Table 7-29.

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Figure 7-32 PWM1 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT1
R/W-X

Table 7-29 PWM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT1	R/W	X	PWM Dutycycle Register Setting for CH1 Load EEPP1 data when reset

7.6.1.15 PWM2 Register (Offset = 22h) [reset = X]

PWM2 is shown in Figure 7-33 and described in Table 7-30.

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Figure 7-33 PWM2 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT2
R/W-X

Table 7-30 PWM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT2	R/W	X	PWM Dutycycle Register Setting for CH2 Load EEPP2 data when reset

7.6.1.16 PWM3 Register (Offset = 23h) [reset = X]

PWM3 is shown in Figure 7-34 and described in Table 7-31.

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Figure 7-34 PWM3 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT3
R/W-X

Table 7-31 PWM3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT3	R/W	X	PWM Dutycycle Register Setting for CH3 Load EEPP3 data when reset

7.6.1.17 PWM4 Register (Offset = 24h) [reset = X]

PWM4 is shown in Figure 7-35 and described in Table 7-32.

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Figure 7-35 PWM4 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT4
R/W-X

Table 7-32 PWM4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT4	R/W	X	PWM Dutycycle Register Setting for CH4 Load EEPP4 data when reset

7.6.1.18 PWM5 Register (Offset = 25h) [reset = X]

PWM5 is shown in Figure 7-36 and described in Table 7-33.

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Figure 7-36 PWM5 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT5
R/W-X

Table 7-33 PWM5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT5	R/W	X	PWM Dutycycle Register Setting for CH5 Load EEPP5 data when reset

7.6.1.19 PWM6 Register (Offset = 26h) [reset = X]

PWM6 is shown in Figure 7-37 and described in Table 7-34.

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Figure 7-37 PWM6 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT6
R/W-X

Table 7-34 PWM6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT6	R/W	X	PWM Dutycycle Register Setting for CH6 Load EEPP6 data when reset

7.6.1.20 PWM7 Register (Offset = 27h) [reset = X]

PWM7 is shown in Figure 7-38 and described in Table 7-35.

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Figure 7-38 PWM7 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT7
R/W-X

Table 7-35 PWM7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT7	R/W	X	PWM Dutycycle Register Setting for CH7 Load EEPP7 data when reset

7.6.1.21 PWM8 Register (Offset = 28h) [reset = X]

PWM8 is shown in Figure 7-39 and described in Table 7-36.

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Figure 7-39 PWM8 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT8
R/W-X

Table 7-36 PWM8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT8	R/W	X	PWM Dutycycle Register Setting for CH8 Load EEPP8 data when reset

7.6.1.22 PWM9 Register (Offset = 29h) [reset = X]

PWM9 is shown in Figure 7-40 and described in Table 7-37.

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Figure 7-40 PWM9 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT9
R/W-X

Table 7-37 PWM9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT9	R/W	X	PWM Dutycycle Register Setting for CH9 Load EEPP9 data when reset

7.6.1.23 PWM10 Register (Offset = 2Ah) [reset = X]

PWM10 is shown in Figure 7-41 and described in Table 7-38.

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Figure 7-41 PWM10 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT10
R/W-X

Table 7-38 PWM10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT10	R/W	X	PWM Dutycycle Register Setting for CH10 Load EEPP10 data when reset

7.6.1.24 PWM11 Register (Offset = 2Bh) [reset = X]

PWM11 is shown in Figure 7-42 and described in Table 7-39.

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Figure 7-42 PWM11 Register

7	6	5	4	3	2	1	0
CONF_PWMOUT11
R/W-X

Table 7-39 PWM11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_PWMOUT11	R/W	X	PWM Dutycycle Register Setting for CH11 Load EEPP11 data when reset

7.6.1.25 PWML0 Register (Offset = 40h) [reset = Fh]

PWML0 is shown in Figure 7-43 and described in Table 7-40.

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Figure 7-43 PWML0 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT0
R-0h				R/W-Fh

Table 7-40 PWML0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT0	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH0

7.6.1.26 PWML1 Register (Offset = 41h) [reset = Fh]

PWML1 is shown in Figure 7-44 and described in Table 7-41.

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Figure 7-44 PWML1 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT1
R-0h				R/W-Fh

Table 7-41 PWML1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT1	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH1

7.6.1.27 PWML2 Register (Offset = 42h) [reset = Fh]

PWML2 is shown in Figure 7-45 and described in Table 7-42.

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Figure 7-45 PWML2 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT2
R-0h				R/W-Fh

Table 7-42 PWML2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT2	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH2

7.6.1.28 PWML3 Register (Offset = 43h) [reset = Fh]

PWML3 is shown in Figure 7-46 and described in Table 7-43.

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Figure 7-46 PWML3 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT3
R-0h				R/W-Fh

Table 7-43 PWML3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT3	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH3

7.6.1.29 PWML4 Register (Offset = 44h) [reset = Fh]

PWML4 is shown in Figure 7-47 and described in Table 7-44.

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Figure 7-47 PWML4 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT4
R-0h				R/W-Fh

Table 7-44 PWML4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT4	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH4

7.6.1.30 PWML5 Register (Offset = 45h) [reset = Fh]

PWML5 is shown in Figure 7-48 and described in Table 7-45.

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Figure 7-48 PWML5 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT5
R-0h				R/W-Fh

Table 7-45 PWML5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT5	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH5

7.6.1.31 PWML6 Register (Offset = 46h) [reset = Fh]

PWML6 is shown in Figure 7-49 and described in Table 7-46.

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Figure 7-49 PWML6 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT6
R-0h				R/W-Fh

Table 7-46 PWML6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT6	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH6

7.6.1.32 PWML7 Register (Offset = 47h) [reset = Fh]

PWML7 is shown in Figure 7-50 and described in Table 7-47.

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Figure 7-50 PWML7 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT7
R-0h				R/W-Fh

Table 7-47 PWML7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT7	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH7

7.6.1.33 PWML8 Register (Offset = 48h) [reset = Fh]

PWML8 is shown in Figure 7-51 and described in Table 7-48.

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Figure 7-51 PWML8 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT8
R-0h				R/W-Fh

Table 7-48 PWML8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT8	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH8

7.6.1.34 PWML9 Register (Offset = 49h) [reset = Fh]

PWML9 is shown in Figure 7-52 and described in Table 7-49.

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Figure 7-52 PWML9 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT9
R-0h				R/W-Fh

Table 7-49 PWML9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT9	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH9

7.6.1.35 PWML10 Register (Offset = 4Ah) [reset = Fh]

PWML10 is shown in Figure 7-53 and described in Table 7-50.

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Figure 7-53 PWML10 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT10
R-0h				R/W-Fh

Table 7-50 PWML10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT10	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH10

7.6.1.36 PWML11 Register (Offset = 4Bh) [reset = Fh]

PWML11 is shown in Figure 7-54 and described in Table 7-51.

Return to the Summary Table.

Figure 7-54 PWML11 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_PWMLOWOUT11
R-0h				R/W-Fh

Table 7-51 PWML11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3-0	CONF_PWMLOWOUT11	R/W	Fh	PWM Dutycycle Register Setting lower 4 bits for CH11

7.6.1.37 CONF_EN0 Register (Offset = 50h) [reset = 0h]

CONF_EN0 is shown in Figure 7-55 and described in Table 7-52.

Return to the Summary Table.

Channel enable settings for channel 0 to 7.

Figure 7-55 CONF_EN0 Register

7	6	5	4	3	2	1	0
CONF_ENCH7	CONF_ENCH6	CONF_ENCH5	CONF_ENCH4	CONF_ENCH3	CONF_ENCH2	CONF_ENCH1	CONF_ENCH0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-52 CONF_EN0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CONF_ENCH7	R/W	0h	Channel 7 enable register. 0h = Disabled 1h = Enabled
6	CONF_ENCH6	R/W	0h	Channel 6 enable register. 0h = Disabled 1h = Enabled
5	CONF_ENCH5	R/W	0h	Channel 5 enable register. 0h = Disabled 1h = Enabled
4	CONF_ENCH4	R/W	0h	Channel 4 enable register. 0h = Disabled 1h = Enabled
3	CONF_ENCH3	R/W	0h	Channel 3 enable register. 0h = Disabled 1h = Enabled
2	CONF_ENCH2	R/W	0h	Channel 2 enable register. 0h = Disabled 1h = Enabled
1	CONF_ENCH1	R/W	0h	Channel 1 enable register. 0h = Disabled 1h = Enabled
0	CONF_ENCH0	R/W	0h	Channel 0 enable register. 0h = Disabled 1h = Enabled

7.6.1.38 CONF_EN1 Register (Offset = 51h) [reset = 0h]

CONF_EN1 is shown in Figure 7-56 and described in Table 7-53.

Return to the Summary Table.

Channel enable settings for channel 8 to 11.

Figure 7-56 CONF_EN1 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_ENCH11	CONF_ENCH10	CONF_ENCH9	CONF_ENCH8
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-53 CONF_EN1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	CONF_ENCH11	R/W	0h	Channel 11 enable register. 0h = Disabled 1h = Enabled
2	CONF_ENCH10	R/W	0h	Channel 10 enable register. 0h = Disabled 1h = Enabled
1	CONF_ENCH9	R/W	0h	Channel 9 enable register. 0h = Disabled 1h = Enabled
0	CONF_ENCH8	R/W	0h	Channel 8 enable register. 0h = Disabled 1h = Enabled

7.6.1.39 CONF_DIAGEN0 Register (Offset = 54h) [reset = X]

CONF_DIAGEN0 is shown in Figure 7-57 and described in Table 7-54.

Return to the Summary Table.

Output diagnostics enable settings for channel 0 to 7.

Figure 7-57 CONF_DIAGEN0 Register

7	6	5	4	3	2	1	0
CONF_DIAGENCH7	CONF_DIAGENCH6	CONF_DIAGENCH5	CONF_DIAGENCH4	CONF_DIAGENCH3	CONF_DIAGENCH2	CONF_DIAGENCH1	CONF_DIAGENCH0
R/W-X	R/W-X	R/W-X	R/W-X	R/W-X	R/W-X	R/W-X	R/W-X

Table 7-54 CONF_DIAGEN0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CONF_DIAGENCH7	R/W	X	Channel 7 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH7 code when reset
6	CONF_DIAGENCH6	R/W	X	Channel 6 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH6 code when reset
5	CONF_DIAGENCH5	R/W	X	Channel 5 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH5 code when reset
4	CONF_DIAGENCH4	R/W	X	Channel 4 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH4 code when reset
3	CONF_DIAGENCH3	R/W	X	Channel 3 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH3 code when reset
2	CONF_DIAGENCH2	R/W	X	Channel 2 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH2 code when reset
1	CONF_DIAGENCH1	R/W	X	Channel 1 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH1 code when reset
0	CONF_DIAGENCH0	R/W	X	Channel 0 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH0 code when reset

7.6.1.40 CONF_DIAGEN1 Register (Offset = 55h) [reset = X]

CONF_DIAGEN1 is shown in Figure 7-58 and described in Table 7-55.

Return to the Summary Table.

Output diagnostics enable settings for channel 8 to 11.

Figure 7-58 CONF_DIAGEN1 Register

7	6	5	4	3	2	1	0
RESERVED				CONF_DIAGENCH11	CONF_DIAGENCH10	CONF_DIAGENCH9	CONF_DIAGENCH8
R-0h				R/W-X	R/W-X	R/W-X	R/W-X

Table 7-55 CONF_DIAGEN1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	CONF_DIAGENCH11	R/W	X	Channel 11 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH11 code when reset
2	CONF_DIAGENCH10	R/W	X	Channel 10 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH10 code when reset
1	CONF_DIAGENCH9	R/W	X	Channel 9 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH9 code when reset
0	CONF_DIAGENCH8	R/W	X	Channel 8 diagnostics enable register. 0h = Disabled 1h = Enabled Load EEP_DIAGENCH8 code when reset

7.6.1.41 CONF_MISC0 Register (Offset = 56h) [reset = X]

CONF_MISC0 is shown in Figure 7-59 and described in Table 7-56.

Return to the Summary Table.

Figure 7-59 CONF_MISC0 Register

7	6	5	4	3	2	1	0
CONF_AUTOSS	CONF_LDO	RESERVED	CONF_EXPEN	RESERVED
R/W-0h	R/W-X	R-0h	R/W-X	R/W-0h

Table 7-56 CONF_MISC0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CONF_AUTOSS	R/W	0h	Auto single-LED short-circuit configuration. 0h = Disabled 1h = Enabled
6	CONF_LDO	R/W	X	LDO output voltage setting. 0h = 5.0V 1h = 4.4V Load EEP_LDO code when reset
5	RESERVED	R	0h	RESERVED
4	CONF_EXPEN	R/W	X	PWM exponetinal dimming enable register. 0h = Disabled 1h = Enabled Load EEP_EXPEN code when reset
3-0	RESERVED	R/W	0h	RESERVED

7.6.1.42 CONF_MISC1 Register (Offset = 57h) [reset = X]

CONF_MISC1 is shown in Figure 7-60 and described in Table 7-57.

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Figure 7-60 CONF_MISC1 Register

7	6	5	4	3	2	1	0
CONF_PWMFREQ				RESERVED		CONF_REFRANGE
R/W-X				R-0h		R/W-X

Table 7-57 CONF_MISC1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CONF_PWMFREQ

R/W

PWM frequency selection register

0h = 200 Hz

1h = 250 Hz

2h = 300 Hz

3h = 350 Hz

4h = 400 Hz

5h = 500 Hz

6h = 600 Hz

7h = 800 Hz

8h = 1000 Hz

9h = 1200 Hz

Ah = 2 kHz

Bh = 4 kHz

Ch = 5.9 kHz

Dh = 7.8 kHz

Eh = 9.6 kHz

Fh = 20.8 kHz
Load EEP_PWMFREQ data when reset

3-2

RESERVED

1-0

CONF_REFRANGE

R/W

Reference current ratio setting register

0h = 64

1h = 128

2h = 256

3h = 512
Load EEP_REFRANGE data when reset

7.6.1.43 CONF_MISC2 Register (Offset = 58h) [reset = X]

CONF_MISC2 is shown in Figure 7-61 and described in Table 7-58.

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Figure 7-61 CONF_MISC2 Register

7	6	5	4	3	2	1	0
RESERVED	CONF_FLTIMEOUT			CONF_ADCLOWSUPTH
R-0h	R/W-X			R/W-X

Table 7-58 CONF_MISC2 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

6-4

CONF_FLTIMEOUT

R/W

FlexWire timeout timer setting register.

0h = 1 ms

1h = 125 µs

2h = 250 µs

3h = 500 µs

4h = 1.25 ms

5h = 2.5 ms

6h = 5 ms

7h = 10 ms
Load EEP_FLTIMEOUT data when reset

3-0

CONF_ADCLOWSUPTH

R/W

ADC Supply monitor threshold setting register.

0h = 5 V

1h = 6 V

2h = 7 V

3h = 8 V

4h = 9 V

5h = 10 V

6h = 11 V

7h = 12 V

8h = 13 V

9h = 14 V

Ah = 15 V

Bh = 16 V

Ch = 17 V

Dh = 18 V

Eh = 19 V

Fh = 20 V
Load EEP_ADCLOWSUPTH data when reset

7.6.1.44 CONF_MISC3 Register (Offset = 59h) [reset = X]

CONF_MISC3 is shown in Figure 7-62 and described in Table 7-59.

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Figure 7-62 CONF_MISC3 Register

7	6	5	4	3	2	1	0
CONF_ODIOUT				CONF_ODPW
R/W-X				R/W-X

Table 7-59 CONF_MISC3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CONF_ODIOUT

R/W

On-demand diagnostics output current setting register.
0x0 to 0xE: IOUT = (CONF_ODIOUT*4+1)/64*I(FULL_RANGE)
0xF: ODIOUT is using its channel setting current
Load EEP_ODIOUT data when reset

3-0

CONF_ODPW

R/W

On-demand diagnostics pulse-width setting EEPROM register.

0h = 100 µs

1h = 20 µs

2h = 30 µs

3h = 50 µs

4h = 80 µs

5h = 150 µs

6h = 200 µs

7h = 300 µs

8h = 500 µs

9h = 800 µs

Ah = 1 ms

Bh = 1.2 ms

Ch = 1.5 ms

Dh = 2 ms

Eh = 3 ms

Fh = 5 ms
Load EEP_ODPW data when reset

7.6.1.45 CONF_MISC4 Register (Offset = 5Ah) [reset = X]

CONF_MISC4 is shown in Figure 7-63 and described in Table 7-60.

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Figure 7-63 CONF_MISC4 Register

7	6	5	4	3	2	1	0
CONF_WDTIMER				RESERVED
R/W-X				R-0h

Table 7-60 CONF_MISC4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CONF_WDTIMER

R/W

Watchdog timer setting EEPROM register.

0h = Disabled, do not automatically enter fail-safe state

1h = 200 µs

2h = 500 µs

3h = 1 ms

4h = 2 ms

5h = 5 ms

6h = 10 ms

7h = 20 ms

8h = 50 ms

9h = 100 ms

Ah = 200 ms

Bh = 500 ms

Ch = 0 µs; direct enter fail-safe state

Dh = 0 µs; direct enter fail-safe state

Eh = 0 µs; direct enter fail-safe state

Fh = 0 µs; direct enter fail-safe state
Load EEP_WDTIMER data when reset

3-0

RESERVED

7.6.1.46 CONF_MISC5 Register (Offset = 5Bh) [reset = X]

CONF_MISC5 is shown in Figure 7-64 and described in Table 7-61.

Return to the Summary Table.

Figure 7-64 CONF_MISC5 Register

7	6	5	4	3	2	1	0
CONF_ADCSHORTTH
R/W-X

Table 7-61 CONF_MISC5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_ADCSHORTTH	R/W	X	ADC short detection threshold setting register. Load EEP_ADCSHORTTH data when rest

7.6.1.47 CLR Register (Offset = 60h) [reset = 0h]

CLR is shown in Figure 7-65 and described in Table 7-62.

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Configuration register for register clear and state configuration

Figure 7-65 CLR Register

7	6	5	4	3	2	1	0
RESERVED		CONF_FORCEFS	CLR_REG	CONF_FORCEERR	CLR_FS	CLR_FAULT	CLR_POR
R-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-62 CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5	CONF_FORCEFS	R/W	0h	Write 1 to force device into Fail-safe state from normal state, automatically reset to 0.
4	CLR_REG	R/W	0h	Write 1 to clear device register settings to default values, automatically reset to 0.
3	CONF_FORCEERR	R/W	0h	Write 1 to force error setting register, automatically reset to 0. 0x0: ERR output = HIGH 0x1: ERR output = LOW;
2	CLR_FS	R/W	0h	Write to force the device out of Fail-safe states to normal state, automatically reset to 0.
1	CLR_FAULT	R/W	0h	Write 1 to clear all fault flags, automatically reset to 0.
0	CLR_POR	R/W	0h	Write 1 to clear POR flag, automatically reset to 0.

7.6.1.48 CONF_LOCK Register (Offset = 61h) [reset = Fh]

CONF_LOCK is shown in Figure 7-66 and described in Table 7-63.

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Configuration register for register lock configuration

Figure 7-66 CONF_LOCK Register

7	6	5	4	3	2	1	0
RESERVED				CONF_CLRLOCK	CONF_CONFLOCK	CONF_IOUTLOCK	CONF_PWMLOCK
R-0h				R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 7-63 CONF_LOCK Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	CONF_CLRLOCK	R/W	1h	CLR register (address 60h) lock bit 0x0: CLR register write-protect disabled. 0x1: CLR register write-protected enabled.
2	CONF_CONFLOCK	R/W	1h	Configuration (CONF_x) registers lock bit 0x0: Configuration setting register write-protect disabled 0x1: Configuration setting register write-protected enabled
1	CONF_IOUTLOCK	R/W	1h	IOUT registers (CONF_IOUTx) lock bit 0x0: Output current setting register write-protect disabled 0x1: Output current setting register write-protected enabled.
0	CONF_PWMLOCK	R/W	1h	PMW dutycyle registers (CONF_PWMOUTx+CONF_PWMLOWOUTx) lock bit 0x0: PWM Register write-protect disabled 0x1: PWM Register write-protected enabled.

7.6.1.49 CONF_MISC6 Register (Offset = 62h) [reset = 0h]

CONF_MISC6 is shown in Figure 7-67 and described in Table 7-64.

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Figure 7-67 CONF_MISC6 Register

7	6	5	4	3	2	1	0
CONF_STAYINEEP	CONF_EEPREADBACK	RESERVED	CONF_ADCCH
R/W-0h	R/W-0h	R-0h	R/W-0h

Table 7-64 CONF_MISC6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CONF_STAYINEEP	R/W	0h	Stay in EEPROM state setting. 0h = EEPROM mode disabled 1h = EEPROM mode enableds
6	CONF_EEPREADBACK	R/W	0h	Setting this bit allow EEPROM to overwrite configuration registers. Automatically returns to 0.
5	RESERVED	R	0h	RESERVED
4-0	CONF_ADCCH	R/W	0h	ADC Channel Selection Register, write this channel will automatically initiate ADC conversion.

7.6.1.50 CONF_MISC7 Register (Offset = 63h) [reset = 0h]

CONF_MISC7 is shown in Figure 7-68 and described in Table 7-65.

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Figure 7-68 CONF_MISC7 Register

7	6	5	4	3	2	1	0
RESERVED		CONF_EXTCLK	CONF_SHAREPWM	RESERVED		CONF_READSHADOW	CONF_EEPMODE
R-0h		R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

Table 7-65 CONF_MISC7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	Reserved
5	CONF_EXTCLK	R/W	0h	External CLK selection 0x0: Use internal clock source for PWM generator 0x1: Use external clock source for PWM generator
4	CONF_SHAREPWM	R/W	0h	Setting all channel PWM dutycycle to be same as CH0 0x0: All channel PWM dutycycle is set independently 0x1: All channel PWM dutycycle is the same as CH0
3-2	RESERVED	R	0h	Reserved
1	CONF_READSHADOW	R/W	0h	Setting EEPROM read back source. 0x0: From EEPROM 0x1: From EEPROM shadow registers
0	CONF_EEPMODE	R/W	0h	EEPROM Programming State Setting. 0x0: Disable EEPMODE Programming State 0x1: Enable EEPMODE Programming State

7.6.1.51 CONF_MISC8 Register (Offset = 64h) [reset = 0h]

CONF_MISC8 is shown in Figure 7-69 and described in Table 7-66.

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Figure 7-69 CONF_MISC8 Register

7	6	5	4	3	2	1	0
CONF_MASKREF	CONF_MASKCRC	CONF_MASKSHORT	CONF_MASKOPEN	CONF_MASKTSD	CONF_EEPPROG	CONF_SSSTART	CONF_INVDIAGSTART
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-66 CONF_MISC8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CONF_MASKREF	R/W	0h	Reference fault mask register. 0x0: Reference fault will be reported to ERR output 0x1: Reference fault will not be reported to ERR output
6	CONF_MASKCRC	R/W	0h	CRC fault mask register. 0x0: CRC fault will be reported to ERR output 0x1: CRC fault will not be reported to ERR output
5	CONF_MASKSHORT	R/W	0h	SHORT fault mask register. 0x0: Short-circuit fault will be reported to ERR output. 0x1: Short-circuit fault will not be reported to ERR output;
4	CONF_MASKOPEN	R/W	0h	OPEN fault mask register. 0x0: Open-circuit fault will be reported to ERR output 0x1: Open-circuit fault will not be reported to ERR output
3	CONF_MASKTSD	R/W	0h	Over temperature shutdown mask to ERR output. 0x0: TSD Fault unmasked to ERR output 0x1: TSD Fault masked to ERR output, output will be shutdown
2	CONF_EEPPROG	R/W	0h	EEPROM burning start in EEPROM mode only, automatically returns to 0
1	CONF_SSSTART	R/W	0h	Single LED Short diagnostics start, automatically returns to 0
0	CONF_INVDIAGSTART	R/W	0h	Invisible Diagnostics start, automatically returns to 0

7.6.1.52 CONF_MISC9 Register (Offset = 65h) [reset = 0h]

CONF_MISC9 is shown in Figure 7-70 and described in Table 7-67.

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Figure 7-70 CONF_MISC9 Register

7	6	5	4	3	2	1	0
CONF_EEPGATE
R/W-0h

Table 7-67 CONF_MISC9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CONF_EEPGATE	R/W	0h	EEPROM Gate for Access Password

7.6.1.53 FLAG0 Register (Offset = 70h) [reset = 3h]

FLAG0 is shown in Figure 7-71 and described in Table 7-68.

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Users read this register to understand if the device is working properly. It includes general fault flags, power, temperature, output failures.

Figure 7-71 FLAG0 Register

7	6	5	4	3	2	1	0
RESERVED	FLAG_REF	FLAG_FS	FLAG_OUT	FLAG_PRETSD	FLAG_TSD	FLAG_POR	FLAG_ERR
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-1h	R-1h

Table 7-68 FLAG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	FLAG_REF	R	0h	Reference fault flag. 0x0: No reference fault is detected. 0x1: Device has reference fault.
5	FLAG_FS	R	0h	Fail-safe flag. 0x0: Device is not in fail-safe mode. 0x1: Device is in fail-safe mode.
4	FLAG_OUT	R	0h	Output fault flag. 0x0: No fault is detected on output channels. 0x1: Device has at least one fault detected on output channels.
3	FLAG_PRETSD	R	0h	Overtemperature pre-shut down flag. 0x0: No over-temperature pre-shutdown is detected. 0x1: Device has triggered over temperature pre-shutdown threshold.
2	FLAG_TSD	R	0h	Overtemperature shut down flag. 0x0: No over-temperature shutdown is detected. 0x1: Device has triggered over temperature shutdown.
1	FLAG_POR	R	1h	Power-on-reset flag. 0x0: No power-on-reset 0x1: Power-on-reset triggered Write 1 to CLEAR_POR will clear the bit
0	FLAG_ERR	R	1h	Error output flag. 0x0: No error flag 0x1: Device has at least one error flag

7.6.1.54 FLAG1 Register (Offset = 71h) [reset = X]

FLAG1 is shown in Figure 7-72 and described in Table 7-69.

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Users read this register to understand if the device is working properly. It includes general fault flags, power, temperature, output failures.

Figure 7-72 FLAG1 Register

7	6	5	4	3	2	1	0
RESERVED		FLAG_EXTFS	FLAG_PROGREADY	FLAG_ADCLOWSUP	FLAG_ADCDONE	FLAG_ODREADY	FLAG_EEPCRC
R-0h		R-X	R-0h	R-0h	R-0h	R-0h	R-X

Table 7-69 FLAG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5	FLAG_EXTFS	R	X	FS pin voltage indicator 0x0: FS pin voltage is logic low 0x1: FS pin voltage is logic high
4	FLAG_PROGREADY	R	0h	EEPROM burning completion flag. 0x0: EEPROM burning not completed or not started 0x1: EEPROM burning completed
3	FLAG_ADCLOWSUP	R	0h	Flag for low supply voltage detection. 0x0: Supply is above preset ADC threshold 0x1: Supply has dropped below preset ADC threshold.
2	FLAG_ADCDONE	R	0h	Flag for ADC conversion completition. 0x0: ADC data not available. 0x1: ADC data available with conversion completed, read ADC_OUT to clear FLAG_ADCDONE.
1	FLAG_ODREADY	R	0h	Flag for on-demand diagnostics. 0x0: on-demand diagnostics not completed or not started. 0x1: on-demand diagnostics completed.
0	FLAG_EEPCRC	R	X	Flag for EEPROM CRC check failure. 0x0: EEPROM CRC passes 0x1: EEPROM CRC check fails

7.6.1.55 FLAG2 Register (Offset = 72h) [reset = X]

FLAG2 is shown in Figure 7-73 and described in Table 7-70.

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ADC conversion output register for supply

Figure 7-73 FLAG2 Register

7	6	5	4	3	2	1	0
ADC_SUPPLY
R-X

Table 7-70 FLAG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_SUPPLY	R	X	ADC conversion output register for supply

7.6.1.56 FLAG3 Register (Offset = 73h) [reset = 0h]

FLAG3 is shown in Figure 7-74 and described in Table 7-71.

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ADC Conversion Output

Figure 7-74 FLAG3 Register

7	6	5	4	3	2	1	0
ADC_OUT
R-0h

Table 7-71 FLAG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_OUT	R	0h	ADC Conversion output register

7.6.1.57 FLAG4 Register (Offset = 74h) [reset = 0h]

FLAG4 is shown in Figure 7-75 and described in Table 7-72.

Return to the Summary Table.

Users read this register to understand if there is any LED open-circuit, LED short-circuit or Single-LED short-circuit fault detected after on-demand diagnostics.

Figure 7-75 FLAG4 Register

7	6	5	4	3	2	1	0
FLAG_ODDIAGCH7	FLAG_ODDIAGCH6	FLAG_ODDIAGCH5	FLAG_ODDIAGCH4	FLAG_ODDIAGCH3	FLAG_ODDIAGCH2	FLAG_ODDIAGCH1	FLAG_ODDIAGCH0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-72 FLAG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FLAG_ODDIAGCH7	R	0h	Channel 7 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
6	FLAG_ODDIAGCH6	R	0h	Channel 6 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
5	FLAG_ODDIAGCH5	R	0h	Channel 5 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
4	FLAG_ODDIAGCH4	R	0h	Channel 4 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
3	FLAG_ODDIAGCH3	R	0h	Channel 3 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
2	FLAG_ODDIAGCH2	R	0h	Channel 2 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
1	FLAG_ODDIAGCH1	R	0h	Channel 1 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
0	FLAG_ODDIAGCH0	R	0h	Channel 0 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected

7.6.1.58 FLAG5 Register (Offset = 75h) [reset = 0h]

FLAG5 is shown in Figure 7-76 and described in Table 7-73.

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Users read this register to understand if there is any LED open-circuit, LED short-circuit or Single-LED short-circuit fault detected after on-demand diagnostics.

Figure 7-76 FLAG5 Register

7	6	5	4	3	2	1	0
RESERVED				FLAG_ODDIAGCH11	FLAG_ODDIAGCH10	FLAG_ODDIAGCH9	FLAG_ODDIAGCH8
R-0h				R-0h	R-0h	R-0h	R-0h

Table 7-73 FLAG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	FLAG_ODDIAGCH11	R	0h	Channel 11 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
2	FLAG_ODDIAGCH10	R	0h	Channel 10 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
1	FLAG_ODDIAGCH9	R	0h	Channel 9 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected
0	FLAG_ODDIAGCH8	R	0h	Channel 8 on-demand diagnostics fault flag bit. 0x0: on-demand diagnostics fault not detected 0x1: on-demand diagnostics fault detected

7.6.1.59 FLAG7 Register (Offset = 77h) [reset = EFh]

FLAG7 is shown in Figure 7-77 and described in Table 7-74.

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EEPROM CRC check reference should be burnt in the end of production line if any EEPROM register is changed.

Figure 7-77 FLAG7 Register

7	6	5	4	3	2	1	0
CALC_EEPCRC
R-B3h

Table 7-74 FLAG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CALC_EEPCRC	R	B3h	EEPROM CRC reference Reset value is 09h for TPS929120A version

7.6.1.60 FLAG8 Register (Offset = 78h) [reset = X]

FLAG8 is shown in Figure 7-78 and described in Table 7-75.

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Calculated CRC result

Figure 7-78 FLAG8 Register

7	6	5	4	3	2	1	0
CALC_CONFCRC
R-X

Table 7-75 FLAG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CALC_CONFCRC	R	X	Calculated CRC result for all CONFx registers

7.6.1.61 FLAG11 Register (Offset = 7Bh) [reset = 0h]

FLAG11 is shown in Figure 7-79 and described in Table 7-76.

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Users read this register to understand if there is any LED open-circuit fault detected.

Figure 7-79 FLAG11 Register

7	6	5	4	3	2	1	0
FLAG_OPENCH7	FLAG_OPENCH6	FLAG_OPENCH5	FLAG_OPENCH4	FLAG_OPENCH3	FLAG_OPENCH2	FLAG_OPENCH1	FLAG_OPENCH0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-76 FLAG11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FLAG_OPENCH7	R	0h	Channel 7 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
6	FLAG_OPENCH6	R	0h	Channel 6 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
5	FLAG_OPENCH5	R	0h	Channel 5 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
4	FLAG_OPENCH4	R	0h	Channel 4 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
3	FLAG_OPENCH3	R	0h	Channel 3 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
2	FLAG_OPENCH2	R	0h	Channel 2 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
1	FLAG_OPENCH1	R	0h	Channel 1 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
0	FLAG_OPENCH0	R	0h	Channel 1 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected

7.6.1.62 FLAG12 Register (Offset = 7Ch) [reset = 0h]

FLAG12 is shown in Figure 7-80 and described in Table 7-77.

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Users read this register to understand if there is any LED open-circuit fault detected.

Figure 7-80 FLAG12 Register

7	6	5	4	3	2	1	0
RESERVED				FLAG_OPENCH11	FLAG_OPENCH10	FLAG_OPENCH9	FLAG_OPENCH8
R-0h				R-0h	R-0h	R-0h	R-0h

Table 7-77 FLAG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	FLAG_OPENCH11	R	0h	Channel 11 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
2	FLAG_OPENCH10	R	0h	Channel 10 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
1	FLAG_OPENCH9	R	0h	Channel 9 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected
0	FLAG_OPENCH8	R	0h	Channel 8 open-circuit fault flag bit. 0x0: open-circuit fault not detected 0x1: open-circuit fault detected

7.6.1.63 FLAG13 Register (Offset = 7Dh) [reset = 0h]

FLAG13 is shown in Figure 7-81 and described in Table 7-78.

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Users read this register to understand if there is any LED short-circuit fault detected.

Figure 7-81 FLAG13 Register

7	6	5	4	3	2	1	0
FLAG_SHORTCH7	FLAG_SHORTCH6	FLAG_SHORTCH5	FLAG_SHORTCH4	FLAG_SHORTCH3	FLAG_SHORTCH2	FLAG_SHORTCH1	FLAG_SHORTCH0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-78 FLAG13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FLAG_SHORTCH7	R	0h	Channel 7 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
6	FLAG_SHORTCH6	R	0h	Channel 6 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
5	FLAG_SHORTCH5	R	0h	Channel 5 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
4	FLAG_SHORTCH4	R	0h	Channel 4 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
3	FLAG_SHORTCH3	R	0h	Channel 3 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
2	FLAG_SHORTCH2	R	0h	Channel 2 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
1	FLAG_SHORTCH1	R	0h	Channel 1 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
0	FLAG_SHORTCH0	R	0h	Channel 0 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected

7.6.1.64 FLAG14 Register (Offset = 7Eh) [reset = 0h]

FLAG14 is shown in Figure 7-82 and described in Table 7-79.

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Users read this register to understand if there is any LED short-circuit fault detected.

Figure 7-82 FLAG14 Register

7	6	5	4	3	2	1	0
RESERVED				FLAG_SHORTCH11	FLAG_SHORTCH10	FLAG_SHORTCH9	FLAG_SHORTCH8
R-0h				R-0h	R-0h	R-0h	R-0h

Table 7-79 FLAG14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	FLAG_SHORTCH11	R	0h	Channel 11 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
2	FLAG_SHORTCH10	R	0h	Channel 10 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected
1	FLAG_SHORTCH9	R	0h	Channel 9 short-circuit fault flag bit. 0b: short-circuit fault not detected 0x1: short-circuit fault detected
0	FLAG_SHORTCH8	R	0h	Channel 8 short-circuit fault flag bit. 0x0: short-circuit fault not detected 0x1: short-circuit fault detected

7.6.1.65 EEPI0 Register (Offset = 80h) [reset = 3Fh]

EEPI0 is shown in Figure 7-83 and described in Table 7-80.

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EEPROM Output Current Setting for CH0

Figure 7-83 EEPI0 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT0
R-0h		R/W-3Fh

Table 7-80 EEPI0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT0	R/W	3Fh	Output current setting for OUT0

7.6.1.66 EEPI1 Register (Offset = 81h) [reset = 3Fh]

EEPI1 is shown in Figure 7-84 and described in Table 7-81.

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EEPROM Output Current Setting for CH1

Figure 7-84 EEPI1 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT1
R-0h		R/W-3Fh

Table 7-81 EEPI1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT1	R/W	3Fh	Output current setting for OUT1

7.6.1.67 EEPI2 Register (Offset = 82h) [reset = 3Fh]

EEPI2 is shown in Figure 7-85 and described in Table 7-82.

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EEPROM Output Current Setting for CH2

Figure 7-85 EEPI2 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT2
R-0h		R/W-3Fh

Table 7-82 EEPI2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT2	R/W	3Fh	Output current setting for OUT2

7.6.1.68 EEPI3 Register (Offset = 83h) [reset = 3Fh]

EEPI3 is shown in Figure 7-86 and described in Table 7-83.

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EEPROM Output Current Setting for CH3

Figure 7-86 EEPI3 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT3
R-0h		R/W-3Fh

Table 7-83 EEPI3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT3	R/W	3Fh	Output current setting for OUT3

7.6.1.69 EEPI4 Register (Offset = 84h) [reset = 3Fh]

EEPI4 is shown in Figure 7-87 and described in Table 7-84.

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EEPROM Output Current Setting for CH4

Figure 7-87 EEPI4 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT4
R-0h		R/W-3Fh

Table 7-84 EEPI4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT4	R/W	3Fh	Output current setting for OUT4

7.6.1.70 EEPI5 Register (Offset = 85h) [reset = 3Fh]

EEPI5 is shown in Figure 7-88 and described in Table 7-85.

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EEPROM Output Current Setting for CH5

Figure 7-88 EEPI5 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT5
R-0h		R/W-3Fh

Table 7-85 EEPI5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT5	R/W	3Fh	Output current setting for OUT5

7.6.1.71 EEPI6 Register (Offset = 86h) [reset = 3Fh]

EEPI6 is shown in Figure 7-89 and described in Table 7-86.

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EEPROM Output Current Setting for CH6

Figure 7-89 EEPI6 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT6
R-0h		R/W-3Fh

Table 7-86 EEPI6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT6	R/W	3Fh	Output current setting for OUT6

7.6.1.72 EEPI7 Register (Offset = 87h) [reset = 3Fh]

EEPI7 is shown in Figure 7-90 and described in Table 7-87.

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EEPROM Output Current Setting for CH7

Figure 7-90 EEPI7 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT7
R-0h		R/W-3Fh

Table 7-87 EEPI7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT7	R/W	3Fh	Output current setting for OUT7

7.6.1.73 EEPI8 Register (Offset = 88h) [reset = 3Fh]

EEPI8 is shown in Figure 7-91 and described in Table 7-88.

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EEPROM Output Current Setting for CH8

Figure 7-91 EEPI8 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT8
R-0h		R/W-3Fh

Table 7-88 EEPI8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT8	R/W	3Fh	Output current setting for OUT8

7.6.1.74 EEPI9 Register (Offset = 89h) [reset = 3Fh]

EEPI9 is shown in Figure 7-92 and described in Table 7-89.

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EEPROM Output Current Setting for CH9

Figure 7-92 EEPI9 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT9
R-0h		R/W-3Fh

Table 7-89 EEPI9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT9	R/W	3Fh	Output current setting for OUT9

7.6.1.75 EEPI10 Register (Offset = 8Ah) [reset = 3Fh]

EEPI10 is shown in Figure 7-93 and described in Table 7-90.

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EEPROM Output Current Setting for CH10

Figure 7-93 EEPI10 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT10
R-0h		R/W-3Fh

Table 7-90 EEPI10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT10	R/W	3Fh	Output current setting for OUT10

7.6.1.76 EEPI11 Register (Offset = 8Bh) [reset = 3Fh]

EEPI11 is shown in Figure 7-94 and described in Table 7-91.

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EEPROM Output Current Setting for CH11

Figure 7-94 EEPI11 Register

7	6	5	4	3	2	1	0
RESERVED		EEP_IOUT11
R-0h		R/W-3Fh

Table 7-91 EEPI11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-0	EEP_IOUT11	R/W	3Fh	Output current setting for OUT11

7.6.1.77 EEPP0 Register (Offset = A0h) [reset = FFh]

EEPP0 is shown in Figure 7-95 and described in Table 7-92.

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EEPROM Output PWM Duty-cycle Setting for CH0

Figure 7-95 EEPP0 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT0
R/W-FFh

Table 7-92 EEPP0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT0	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH0

7.6.1.78 EEPP1 Register (Offset = A1h) [reset = FFh]

EEPP1 is shown in Figure 7-96 and described in Table 7-93.

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EEPROM Output PWM Duty-cycle Setting for CH1

Figure 7-96 EEPP1 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT1
R/W-FFh

Table 7-93 EEPP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT1	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH1

7.6.1.79 EEPP2 Register (Offset = A2h) [reset = FFh]

EEPP2 is shown in Figure 7-97 and described in Table 7-94.

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EEPROM Output PWM Duty-cycle Setting for CH2

Figure 7-97 EEPP2 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT2
R/W-FFh

Table 7-94 EEPP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT2	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH2

7.6.1.80 EEPP3 Register (Offset = A3h) [reset = FFh]

EEPP3 is shown in Figure 7-98 and described in Table 7-95.

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EEPROM Output PWM Duty-cycle Setting for CH3

Figure 7-98 EEPP3 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT3
R/W-FFh

Table 7-95 EEPP3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT3	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH3

7.6.1.81 EEPP4 Register (Offset = A4h) [reset = FFh]

EEPP4 is shown in Figure 7-99 and described in Table 7-96.

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EEPROM Output PWM Duty-cycle Setting for CH4

Figure 7-99 EEPP4 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT4
R/W-FFh

Table 7-96 EEPP4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT4	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH4

7.6.1.82 EEPP5 Register (Offset = A5h) [reset = FFh]

EEPP5 is shown in Figure 7-100 and described in Table 7-97.

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EEPROM Output PWM Duty-cycle Setting for CH5

Figure 7-100 EEPP5 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT5
R/W-FFh

Table 7-97 EEPP5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT5	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH5

7.6.1.83 EEPP6 Register (Offset = A6h) [reset = FFh]

EEPP6 is shown in Figure 7-101 and described in Table 7-98.

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EEPROM Output PWM Duty-cycle Setting for CH6

Figure 7-101 EEPP6 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT6
R/W-FFh

Table 7-98 EEPP6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT6	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH6

7.6.1.84 EEPP7 Register (Offset = A7h) [reset = FFh]

EEPP7 is shown in Figure 7-102 and described in Table 7-99.

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EEPROM Output PWM Duty-cycle Setting for CH7

Figure 7-102 EEPP7 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT7
R/W-FFh

Table 7-99 EEPP7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT7	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH7

7.6.1.85 EEPP8 Register (Offset = A8h) [reset = FFh]

EEPP8 is shown in Figure 7-103 and described in Table 7-100.

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EEPROM Output PWM Duty-cycle Setting for CH8

Figure 7-103 EEPP8 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT8
R/W-FFh

Table 7-100 EEPP8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT8	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH8

7.6.1.86 EEPP9 Register (Offset = A9h) [reset = FFh]

EEPP9 is shown in Figure 7-104 and described in Table 7-101.

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EEPROM Output PWM Duty-cycle Setting for CH9

Figure 7-104 EEPP9 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT9
R/W-FFh

Table 7-101 EEPP9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT9	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH9

7.6.1.87 EEPP10 Register (Offset = AAh) [reset = FFh]

EEPP10 is shown in Figure 7-105 and described in Table 7-102.

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EEPROM Output PWM Duty-cycle Setting for CH10

Figure 7-105 EEPP10 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT10
R/W-FFh

Table 7-102 EEPP10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT10	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH10

7.6.1.88 EEPP11 Register (Offset = ABh) [reset = FFh]

EEPP11 is shown in Figure 7-106 and described in Table 7-103.

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EEPROM Output PWM Duty-cycle Setting for CH11

Figure 7-106 EEPP11 Register

7	6	5	4	3	2	1	0
EEP_PWMOUT11
R/W-FFh

Table 7-103 EEPP11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_PWMOUT11	R/W	FFh	PWM Dutycycle EEPROM Register Setting for CH11

7.6.1.89 EEPM0 Register (Offset = C0h) [reset = 0h]

EEPM0 is shown in Figure 7-107 and described in Table 7-104.

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Channel enable setting in fail-safe state 0 for channel 0 to 7.

Figure 7-107 EEPM0 Register

7	6	5	4	3	2	1	0
EEP_FS0CH7	EEP_FS0CH6	EEP_FS0CH5	EEP_FS0CH4	EEP_FS0CH3	EEP_FS0CH2	EEP_FS0CH1	EEP_FS0CH0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-104 EEPM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EEP_FS0CH7	R/W	0h	CH7 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
6	EEP_FS0CH6	R/W	0h	CH6 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
5	EEP_FS0CH5	R/W	0h	CH5 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
4	EEP_FS0CH4	R/W	0h	CH4 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
3	EEP_FS0CH3	R/W	0h	CH3 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
2	EEP_FS0CH2	R/W	0h	CH2 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
1	EEP_FS0CH1	R/W	0h	CH1 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
0	EEP_FS0CH0	R/W	0h	CH0 setting in fail-safe state 0. 0h = Disabled 1h = Enabled

7.6.1.90 EEPM1 Register (Offset = C1h) [reset = 0h]

EEPM1 is shown in Figure 7-108 and described in Table 7-105.

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Channel enable setting in fail-safe state 0 for channel 8 to 11.

Figure 7-108 EEPM1 Register

7	6	5	4	3	2	1	0
RESERVED				EEP_FS0CH11	EEP_FS0CH10	EEP_FS0CH9	EEP_FS0CH8
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-105 EEPM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	EEP_FS0CH11	R/W	0h	CH11 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
2	EEP_FS0CH10	R/W	0h	CH10 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
1	EEP_FS0CH9	R/W	0h	CH9 setting in fail-safe state 0. 0h = Disabled 1h = Enabled
0	EEP_FS0CH8	R/W	0h	CH8 setting in fail-safe state 0. 0h = Disabled 1h = Enabled

7.6.1.91 EEPM2 Register (Offset = C2h) [reset = FFh]

EEPM2 is shown in Figure 7-109 and described in Table 7-106.

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Channel enable setting in fail-safe state 1 for channel 0 to 7.

Figure 7-109 EEPM2 Register

7	6	5	4	3	2	1	0
EEP_FS1CH7	EEP_FS1CH6	EEP_FS1CH5	EEP_FS1CH4	EEP_FS1CH3	EEP_FS1CH2	EEP_FS1CH1	EEP_FS1CH0
R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 7-106 EEPM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EEP_FS1CH7	R/W	1h	CH7 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
6	EEP_FS1CH6	R/W	1h	CH6 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
5	EEP_FS1CH5	R/W	1h	CH5 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
4	EEP_FS1CH4	R/W	1h	CH4 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
3	EEP_FS1CH3	R/W	1h	CH3 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
2	EEP_FS1CH2	R/W	1h	CH2 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
1	EEP_FS1CH1	R/W	1h	CH1 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
0	EEP_FS1CH0	R/W	1h	CH0 setting in fail-safe state 1. 0h = Disabled 1h = Enabled

7.6.1.92 EEPM3 Register (Offset = C3h) [reset = Fh]

EEPM3 is shown in Figure 7-110 and described in Table 7-107.

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Channel enable setting in fail-safe state 1 for channel 8 to 11.

Figure 7-110 EEPM3 Register

7	6	5	4	3	2	1	0
RESERVED				EEP_FS1CH11	EEP_FS1CH10	EEP_FS1CH9	EEP_FS1CH8
R-0h				R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 7-107 EEPM3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	EEP_FS1CH11	R/W	1h	CH11 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
2	EEP_FS1CH10	R/W	1h	CH10 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
1	EEP_FS1CH9	R/W	1h	CH9 setting in fail-safe state 1. 0h = Disabled 1h = Enabled
0	EEP_FS1CH8	R/W	1h	CH8 setting in fail-safe state 1. 0h = Disabled 1h = Enabled

7.6.1.93 EEPM4 Register (Offset = C4h) [reset = FFh]

EEPM4 is shown in Figure 7-111 and described in Table 7-108.

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Figure 7-111 EEPM4 Register

7	6	5	4	3	2	1	0
EEP_DIAGENCH7	EEP_DIAGENCH6	EEP_DIAGENCH5	EEP_DIAGENCH4	EEP_DIAGENCH3	EEP_DIAGENCH2	EEP_DIAGENCH1	EEP_DIAGENCH0
R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 7-108 EEPM4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EEP_DIAGENCH7	R/W	1h	Channel 7 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
6	EEP_DIAGENCH6	R/W	1h	Channel 6 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
5	EEP_DIAGENCH5	R/W	1h	Channel 5 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
4	EEP_DIAGENCH4	R/W	1h	Channel 4 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
3	EEP_DIAGENCH3	R/W	1h	Channel 3 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
2	EEP_DIAGENCH2	R/W	1h	Channel 2 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
1	EEP_DIAGENCH1	R/W	1h	Channel 1 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
0	EEP_DIAGENCH0	R/W	1h	Channel 0 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled

7.6.1.94 EEPM5 Register (Offset = C5h) [reset = Fh]

EEPM5 is shown in Figure 7-112 and described in Table 7-109.

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Figure 7-112 EEPM5 Register

7	6	5	4	3	2	1	0
RESERVED				EEP_DIAGENCH11	EEP_DIAGENCH10	EEP_DIAGENCH9	EEP_DIAGENCH8
R-0h				R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 7-109 EEPM5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	RESERVED
3	EEP_DIAGENCH11	R/W	1h	Channel 11 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
2	EEP_DIAGENCH10	R/W	1h	Channel 10 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
1	EEP_DIAGENCH9	R/W	1h	Channel 9 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled
0	EEP_DIAGENCH8	R/W	1h	Channel 8 diagnostics enable EEPROM register. 0h = Disabled 1h = Enabled

7.6.1.95 EEPM6 Register (Offset = C6h) [reset = 0h]

EEPM6 is shown in Figure 7-113 and described in Table 7-110.

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Figure 7-113 EEPM6 Register

7	6	5	4	3	2	1	0
RESERVED	EEP_LDO	RESERVED	EEP_EXPEN	EEP_DEVADDR
R-0h	R/W-0h	R-0h	R/W-0h	R/W-0h

Table 7-110 EEPM6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	EEP_LDO	R/W	0h	LDO output voltage setting. 0h = 5.0 V 1h = 4.4 V
5	RESERVED	R	0h	RESERVED
4	EEP_EXPEN	R/W	0h	PWM generator exponetinal dimmng enable register. 0h = Disabled 1h = Enabled
3-0	EEP_DEVADDR	R/W	0h	Device slave address EEPROM register 0h = slave address is 0000b 1h = slave address is 0001b 2h = slave address is 0010b 3h = slave address is 0011b 4h = slave address is 0100b 5h = slave address is 0101b 6h = slave address is 0110b 7h = slave address is 0111b 8h = slave address is 1000b 9h = slave address is 1001b Ah = slave address is 1010b Bh = slave address is 1011b Ch = slave address is 1100b Dh = slave address is 1101b Eh = slave address is 1110b Fh = slave address is 1111b Reset value is 8h for TPS929120A version

7.6.1.96 EEPM7 Register (Offset = C7h) [reset = A7h]

EEPM7 is shown in Figure 7-114 and described in Table 7-111.

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Figure 7-114 EEPM7 Register

7	6	5	4	3	2	1	0
EEP_PWMFREQ				EEP_INTADDR	EEP_OFAF	EEP_REFRANGE
R/W-Ah				R/W-0h	R/W-1h	R/W-3h

Table 7-111 EEPM7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	EEP_PWMFREQ	R/W	Ah	PWM frequency selection EEPROM register 0h = 200 Hz 1h = 250 Hz 2h = 300 Hz 3h = 350 Hz 4h = 400 Hz 5h = 500 Hz 6h = 600 Hz 7h = 800 Hz 8h = 1000 Hz 9h = 1200 Hz Ah = 2 kHz Bh = 4 kHz Ch = 5.9 kHz Dh = 7.8 kHz Eh = 9.6 kHz Fh = 20.8 kHz
3	EEP_INTADDR	R/W	0h	Slave address selection bit. 0x0: Deivce slave address set by ADDR2/ADDR1/ADDR0 pins configuration 0x1: Device slave address set by EEP_DEVADDR EEPROM register
2	EEP_OFAF	R/W	1h	Output failure state setting. 0x0: One-fails-others-on. 0x1: One-fails-all-fail.
1-0	EEP_REFRANGE	R/W	3h	Reference current ratio setting EEPROM register 0h = 64 1h = 128 2h = 256 3h = 512

7.6.1.97 EEPM8 Register (Offset = C8h) [reset = 3h]

EEPM8 is shown in Figure 7-115 and described in Table 7-112.

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Figure 7-115 EEPM8 Register

7	6	5	4	3	2	1	0
RESERVED	EEP_FLTIMEOUT			EEP_ADCLOWSUPTH
R-0h	R/W-0h			R/W-3h

Table 7-112 EEPM8 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

REVSERVED

6-4

EEP_FLTIMEOUT

R/W

FlexWire timeout timer setting EEPROM register.

0h = 1 ms

1h = 125 µs

2h = 250 µs

3h = 500 µs

4h = 1.25 ms

5h = 2.5 ms

6h = 5 ms

7h = 10 ms

3-0

EEP_ADCLOWSUPTH

R/W

ADC Supply monitor threshold setting EEPROM register.

0h = 5 V

1h = 6 V

2h = 7 V

3h = 8 V

4h = 9 V

5h = 10 V

6h = 11 V

7h = 12 V

8h = 13 V

9h = 14 V

Ah = 15 V

Bh = 16 V

Ch = 17 V

Dh = 18 V

Eh = 19 V

Fh = 20 V

7.6.1.98 EEPM9 Register (Offset = C9h) [reset = 0h]

EEPM9 is shown in Figure 7-116 and described in Table 7-113.

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Figure 7-116 EEPM9 Register

7	6	5	4	3	2	1	0
EEP_ODIOUT				EEP_ODPW
R/W-0h				R/W-0h

Table 7-113 EEPM9 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

EEP_ODIOUT

R/W

On-demand diagnostics output current setting EEPROM register.
0x0 to 0xE: IOUT = (CONF_ODIOUT*4+1)/64*I(FULL_RANGE)
0xF: ODIOUT is using its channel setting current

3-0

EEP_ODPW

R/W

On-demand diagnostics pulse-width setting EEPROM register.

0h = 100 µs

1h = 20 µs

2h = 30 µs

3h = 50 µs

4h = 80 µs

5h = 150 µs

6h = 200 µs

7h = 300 µs

8h = 500 µs

9h = 800 µs

Ah = 1 ms

Bh = 1.2 ms

Ch = 1.5 ms

Dh = 2 ms

Eh = 3 ms

Fh = 5 ms

7.6.1.99 EEPM10 Register (Offset = CAh) [reset = 0h]

EEPM10 is shown in Figure 7-117 and described in Table 7-114.

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Figure 7-117 EEPM10 Register

7	6	5	4	3	2	1	0
EEP_WDTIMER				EEP_INITTIMER
R/W-0h				R/W-0h

Table 7-114 EEPM10 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

EEP_WDTIMER

R/W

Watchdog timer setting EEPROM register.

0h = Disabled, do not automatically enter fail-safe state

1h = 200 µs

2h = 500 µs

3h = 1 ms

4h = 2 ms

5h = 5 ms

6h = 10 ms

7h = 20 ms

8h = 50 ms

9h = 100 ms

Ah = 200 ms

Bh = 500 ms

Ch = 0 µs; direct enter fail-safe state

Dh = 0 µs; direct enter fail-safe state

Eh = 0 µs; direct enter fail-safe state

Fh = 0 µs; direct enter fail-safe state

3-0

EEP_INITTIMER

R/W

Initialization timer setting EEPROM register.

0h = 0 ms

1h = 50 ms

2h = 20 ms

3h = 10 ms

4h = 5 ms

5h = 2 ms

6h = 1 ms

7h = 500 µs

8h = 200 µs

9h = 100 µs

Ah = 50 µs

Bh = 50 µs

Ch = 50 µs

Dh = 50 µs

Eh = 50 µs

Fh = 50 µs

7.6.1.100 EEPM11 Register (Offset = CBh) [reset = 0h]

EEPM11 is shown in Figure 7-118 and described in Table 7-115.

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Figure 7-118 EEPM11 Register

7	6	5	4	3	2	1	0
EEP_ADCSHORTTH
R/W-0h

Table 7-115 EEPM11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_ADCSHORTTH	R/W	0h	ADC short detection threshold setting EEPROM register

7.6.1.101 EEPM15 Register (Offset = CFh) [reset = 23h]

EEPM15 is shown in Figure 7-119 and described in Table 7-116.

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Figure 7-119 EEPM15 Register

7	6	5	4	3	2	1	0
EEP_CRC
R/W-B3h

Table 7-116 EEPM15 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EEP_CRC	R/W	B3h	CRC reference for all EEPROM register, manufacture default CRC code is B3h for TPS929120 and 09h for TPS929120A version.