SLVSGM1B July   2023  – June 2024 TPSM828301 , TPSM828302 , TPSM828303

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RDS Package
    5. 6.5 Thermal Information VCB Package
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse Width Modulation (PWM) Operation
      2. 7.3.2 Power Save Mode (PSM) Operation
      3. 7.3.3 Start-Up and Soft Start
      4. 7.3.4 Switch Cycle-by-Cycle Current Limit
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Optimized EMI Performance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Disable, and Output Discharge
      2. 7.4.2 Minimum Duty Cycle and 100% Mode Operation
      3. 7.4.3 Power Good
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

TJ = –40°C to +125°C, VIN = 2.25 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Operating quiescent current EN = VIN, IOUT = 0 mA, VOUT = 1.8 V,  MODE = GND, device not switching 7 17 µA
ISD VIN shutdown supply current EN = low, TJ = –40oC to 85oC 100 700 nA
VUVLO(+) Rising UVLO threshold voltage (VIN) 2.05 2.15 2.25 V
VUVLO(hys) UVLO hysteresis (VIN) 90 120 mV
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold TJ rising 150 °C
TJ(HYS) Thermal shutdown hysteresis 20 °C
LOGIC PINs
VEN(+) High-level input voltage (EN) 0.8 V
VEN(-) Low-level input voltage (EN) 0.35 V
VMODE(+) High-level input voltage (MODE) 0.8 V
VMODE(-) Low-level input voltage (MODE) 0.35 V
IEN(LKG) EN Input leakage current VEN = HIGH 10 100 nA
IMODE(LKG) MODE Input leakage current VMODE = HIGH 10 100 nA
STARTUP
tSS Internal fixed soft-start time From VOUT = 0 to VOUT = 95% 180 300 440 µs
td(EN) Enable delay time From EN HIGH to device starts switching 120 220 µs
REFERENCE VOLTAGE
VFB Feedback voltage accuracy PWM mode 495 500 505 mV
VFB Feedback voltage accuracy PWM mode –1 +1 %
VFB Feedback voltage accuracy PFM mode, COUT,eff ≥ 15 µF, L = 0.47 µH –1 +2 %
IFB(LKG) FB input leakage current, adjustable version VFB = 0.5 V 10 70 nA
IVOS(LKG) VOS input leakage current VEN = low 100 500 nA
POWER GOOD
VPG,UV(+) Rising power-good threshold
voltage (output undervoltage)		 Power Good low, VFB rising 94 96 98 %
VPG,UV(-) Falling power-good threshold
voltage (output undervoltage)		 Power Good high, VFB falling 90 92 94 %
VPG,OV(+) Rising power-good threshold
voltage (output overvoltage)		 Power Good high, VFB rising 108 110 112 %
VPG,OV(-) Falling power-good threshold
voltage (output overvoltage)		 Power Good low, VFB falling 102.5 105 107 %
td(PG) Power good delay at start-up Low-to-high transition on the PG pin at start up 128 µs
td(PG) Power good deglitch delay during operation High-to-low or low-to-high transition on the PG pin 30 45 60 µs
IPG(LKG) PG pin Leakage current when open drain output is high VPG = 5.0 V 10 100 nA
VPG,OL PG pin low-level output voltage IPG = 1 mA  0.4 V
POWER STAGE
RDP
Dropout resistance

 TPSM82830x, VIN ≥ 5 V, 100% mode, TJ = 25°C, VCB package 55 mΩ
RDP
Dropout resistance

 TPSM82830x, VIN ≥ 5 V, 100% mode, TJ = 25°C, RDS package 61 mΩ
RDP
Dropout resistance

 TPSM82830x, VIN = 2.7 V, 100% mode, TJ = 25°C 78 105 mΩ
fSW Switching frequency, PWM mode IOUT = 1 A, VOUT = 1.8 V 2.0 MHz
OVERCURRENT PROTECTION
IHS(OC) High-side peak current limit TPSM828301 1.8 2.1 2.6 A
IHS(OC) High-side peak current limit TPSM828302 2.7 3.3 3.9 A
IHS(OC) High-side peak current limit TPSM828303 4.0 4.6 5.4 A
ILS(NOC) Low-side negative current limit Sinking current limit on LS FET –1.8 A
OUTPUT DISCHARGE
IDIS Output discharge current on SW pin VIN > 2 V, VSW = 0.4 V, EN = LOW 75 400 mA