SLUSDD5A April 2019 – December 2020 UC1825B-SP
PRODUCTION DATA
For most designs, a ripple voltage is picked and the output capacitance is figured out from that value. The output capacitance value needs to be able to withstand a full output current step as well as keep the voltage ripple of the output low. The UC1825B-SP design started similar to that using the equations for voltage ripple and load step with Equation 35 and Equation 37.
A value of around 1145 µF was chosen to keep output voltage ripple low. Note that the output voltage ripple in the design was further decreased by adding an output filter and by adding an inductor after a small portion of the output capacitance. This was done in order to keep output voltage ripple as low as possible. Six ceramic capacitors were picked to be placed before the output filter and then the large tantalum capacitors with some small ceramics were added to be part of the output filter. The initial ceramics will help with the initial current ripple, but have a very large output voltage ripple. This voltage ripple will be attenuated by the inductor and capacitor combination placed between the ceramic capacitors and the output. The equations below allow for finding the amount of attenuation that will come from a specific output filter inductance. An inductance of 500 nH was chosen to attenuate the output voltage ripple. The value was chosen to put the resonant frequency pole well before the switching frequency of the design as well as the zero from the ESR of the bulk capacitors to provide more attenuation.
Sometimes the output filter can cause peaking at high frequencies. This can be damped by adding a resistor in parallel with the inductor which will decrease efficiency. For the UC1825B-SP design 0.5 Ω was used as a very conservative value. The resistance needed to damp the peaking can be calculated using the following equations: