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  • UCC2805x, UCC3805x Transition Mode PFC Controller

    • SLUS515G September   2002  – December 2015 UCC28050 , UCC28051 , UCC38050 , UCC38051

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • UCC2805x, UCC3805x Transition Mode PFC Controller
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO and Reference Block
      2. 7.3.2 Error Amplifier
      3. 7.3.3 Zero Current Detection and Re-Start Timer Blocks
      4. 7.3.4 Enable Block
      5. 7.3.5 Zero Power Block
      6. 7.3.6 Multiplier Block
      7. 7.3.7 Overvoltage Protection (OVP) Block
    4. 7.4 Device Functional Modes
      1. 7.4.1 Transition Mode Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 MOSFET Selection
        3. 8.2.2.3 Diode Selection
        4. 8.2.2.4 Capacitor Selection
        5. 8.2.2.5 Multiplier Set-Up
        6. 8.2.2.6 Sense Resistor Selection
        7. 8.2.2.7 Output Voltage Sense Design
        8. 8.2.2.8 Voltage Loop Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Bias Current
      2. 10.1.2 Zero Current Detection
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information
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  • slus515g_pm
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DATA SHEET

UCC2805x, UCC3805x Transition Mode PFC Controller

1 Features

  • Transition Mode PFC Controller for Low Implementation Cost
  • Industry Pin Compatibility With Improved Feature Set
  • Improved Transient Response With Slew-Rate Comparator
  • Zero Power Detect to Prevent Overvoltage Protection (OVP) During Light Load Conditions
  • Accurate Internal VREF for Tight Output Regulation
  • Two UVLO Options
  • OVP, Open-Feedback Protection, and Enable Circuits
  • ±750-mA Peak Gate Drive Current
  • Low Start-Up and Operating Currents
  • Lead (Pb)-Free Packages

2 Applications

  • Single-Stage PFC Flyback Converters for Lighting and Motor Drives
  • Switch-Mode Power Supplies for Desktops, Monitors, TVs, and Set Top Boxes (STBs)
  • AC Adapter Front-End Power Supplies
  • Electronic Ballasts

3 Description

The UCC38050 and UCC38051 are PFC controllers for low-to-medium power applications requiring compliance with IEC 1000-3-2 harmonic reduction standard. The controllers are designed for a boost preregulator operating in transition mode (also referred to as boundary-conduction mode or critical conduction-mode operation). They feature a transconductance voltage amplifier for feedback error processing, a simple multiplier for generating a current command proportional to the input voltage, a current-sense (PWM) comparator, PWM logic, and a totem-pole driver for driving an external FET.

In the transition mode operation, the PWM circuit is self-oscillating, with the turnon being governed by an inductor zero-current detector (ZCD pin), and the turnoff being governed by the current-sense comparator. Additionally, the controller provides features such as peak current limit, default timer, overvoltage protection (OVP) and enable.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
UCC28050, UCC28051, UCC38050, UCC38051 SOIC (8) 3.91 mm × 4.90 mm
PDIP (8) 6.35 mm × 9.81 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application Diagram

UCC28050 UCC28051 UCC38050 UCC38051 slus515_sch.gif

4 Revision History

Changes from F Revision (March 2009) to G Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

5 Pin Configuration and Functions

D or P Package
8-Pin SOIC or PDIP
Top View
UCC28050 UCC28051 UCC38050 UCC38051 slus515_po.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
COMP 2 O Output of the transconductance error amplifier. Loop compensation components are connected between this pin and ground. The output current capability of this pin is 10-μA under normal conditions, but increases to approximately 1-mA when the differential input is greater than the specified values in the specifications table. This voltage is one of the inputs to the multiplier, with a dynamic input range of 2.5 V to 3.8 V. During zero power or overvoltage conditions, this pin goes below 2.5 V nominal. When it goes below 2.3 V, the zero power comparator is activated, which prevents the gate drive from switching.
CS 4 I This pin senses the instantaneous switch current in the boost switch and uses it as the internal ramp for PWM comparator. The internal circuitry filters out switching noise spikes without requiring external components. In addition, an external R-C filter may be required to suppress the noise spikes. An internal clamp on the multiplier output terminates the switching cycle if this pin voltage exceeds 1.7 V. Additional external filtering may be required. CS threshold is approximately equal to:
Equation 1. UCC28050 UCC28051 UCC38050 UCC38051 slus515_eq1.gif
VOFFSET is approximately 75 mV to improve the zero crossing distortion.
DRV 7 O The gate drive output for an external boost switch. This output is capable of delivering up to 750-mA peak currents during turn-on and turn-off. An external gate drive resistor may be needed to limit the peak current depending on the VCC voltage being used. Below the UVLO threshold, the output is held low.
GND 6 – The chip reference ground. All bypassing elements are connected to ground pin with shortest loops feasible.
MULTIN 3 I This pin senses the instantaneous boost regulator input voltage through a voltage divider. The voltage acts as one of the inputs to the internal multiplier. Recommended operating range is 0 V to 2.5 V at high line.
VCC 8 – The supply voltage for the chip. This pin should be bypassed with a high-frequency capacitor (greater than 0.1-μF) and tied to GND. The UCC38050 has a wide UVLO hysteresis of approximately 6.3 V that allows use of a lower value supply capacitor on this pin for quicker and easier start-up. The UCC38051 has a narrow UVLO hysteresis with of about 2.8 V, and a start-up voltage of about 12.5 V for applications where the operation of the PFC device must be controlled by a downstream PWM controller.
VO_SNS 1 I This pin senses the boost regulator output voltage through a voltage divider. Internally, this pin is the inverting input to the transconductance amplifier (with a nominal value of 2.5 V) and also is input to the OVP comparator. Additionally, pulling this pin below the ENABLE threshold turns off the output switching, ensuring that the gate drive is held off while the boost output is pre-charging, and also ensuring no runaway if the feedback path is open.
ZCD 5 I Input for the zero current detect comparator. The boost inductor current is indirectly sensed through the bias winding on the boost inductor. The ZCD pin input goes low when the inductor current reaches zero and that transition is detected. Internal active voltage clamps are provided to prevent this pin from going below ground or too high. If zero current is not detected within 400 μs, a reset timer sets the latch and gate drive.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC (Internally clamped) 20 V
Input current into VCC clamp IDD 30 mA
Input current ZCD ±10 mA
Gate drive current (peak), IDRV DRV ±750 mA
Input voltage, VCC VO_SNS, MULTIN, CS 5 V
Maximum negative voltage VO_SNS, MULTIN, DRV, CS –0.5 V
Power dissipation at TA = 50°C D package 650 mW
P package 1 W
Operating junction temperature range, TJ –55 150 °C
Storage temperature, Tstg –65 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
SOIC PACKAGE
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC input voltage from a low-impedance source VCCOFF + 1 V 18 V
Operating junction temperature, TJ –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) UCC2805x, UCC3805x UNIT
D (SOIC) P (PDIP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 113.6 55.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 60.3 45.5 °C/W
RθJB Junction-to-board thermal resistance 54.3 32.7 °C/W
ψJT Junction-to-top characterization parameter 14 23.1 °C/W
ψJB Junction-to-board characterization parameter 53.8 32.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 0°C to 70°C for the UCC3805x, –40°C to +105°C for the UCC2805x, TA = TJ, VCC = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VCC operating voltage 18 V
Shunt voltage IVCC = 25 mA 18 19 20 V
Supply current, off VCC = VCC turnon threshold –300 mV 75 125 µA
Supply current, disabled VO_SNS = 0.5 V 2 4 mA
Supply current, on 75 kHz, CL = 0 nF 4 6 mA
Supply current, dynamic operating 75 kHz, CL = 1 nF 5 7 mA
UVLO
VCC turnon threshold UCCx8050 15.4 15.8 16.4 V
UCCx8051 12 12.5 13
VCC turnoff threshold 9.4 9.7 10 V
UVLO hysteresis UCCx8050 5.8 6.3 6.8 V
UCCx8051 2.3 2.8 3.3
VOLTAGE AMPLIFIER (VO_SNS)
Input voltage (VREF) UCC3805x 2.46 2.5 2.54 V
UCC2805x 2.45 2.5 2.55
Input bias current 0.5 µA
VCOMP high VO_SNS = 2.1 V 4.5 5.5 V
VCOMP low VO_SNS = 2.55 V 1.8 2.45 V
gM TJ = 25 °C, VCOMP = 3.5 V 60 90 130 µS
Source current UCCx8050 VO_SNS = 2.1 V, VCOMP = 3.5 V –0.2 –0.1 mA
UCCx8051 VO_SNS = 2.1 V, VCOMP = 2.5 V –200 –300 –400 µA
Sink current VO_SNS = 2.7 V, VCOMP = 3.5 V 0.2 1 mA
OVER VOLTAGE PROTECTION / ENABLE
Overvoltage reference UCCx8050 VREF + 0.165 VREF + 0.19 VREF + 0.21 V
UCCx8051 VREF + 0.15 VREF + 0.18 VREF + 0.21
Hysteresis UCCx8050 175 200 225 mV
UCCx8051 150 180 210
Enable threshold UCCx8050 0.62 0.67 0.72 V
UCCx8051 0.18 0.23 0.28
Enable hysteresis 0.05 0.1 0.2 V
MULTIPLIER
Multiplier gain constant (k) VMULTIN = 0.5 V, COMP = 3.5 V 0.43 0.65 0.87 1/V
Dynamic input range, VMULTIN INPUT 0 to 2.5 0 to 3.5 V
Dynamic input range, COMP INPUT 2.5 to 3.8 2.5 to 4 V
Input bias current, MULTIN 0.1 1 µA
ZERO POWER
Zero power comparator threshold(1) Measured on VCOMP 2.1 2.3 2.5 V
ZERO CURRENT DETECT
Input threshold (rising edge)(1) 1.5 1.7 2 V
Hysteresis(1) 250 350 450 mV
Input high clamp I = 3 mA 5 6 V
Input low clamp I = −3 mA 0.3 0.65 0.9 V
Restart time delay 200 400 µs
CURRENT SENSE COMPARATOR
Input bias current CS = 0 V 0.1 1 µA
Input offset voltage(1) –10 10 mV
Delay to output CS to DRV 300 450 ns
Maximum current sense threshold voltage 1.55 1.7 1.8 V
PFC GATE DRIVER
GT1 pull-up resistance IOUT = –125 mA 5 12 Ω
GT1 pull-down resistance IOUT = 125 mA 2 10 Ω
GT1 output rise time CLOAD = 1 nF, RLOAD = 10 Ω 25 75 ns
GT1 output fall time CLOAD = 1 nF, RLOAD = 10 Ω 10 50 ns
(1) Ensured by design. Not production tested.

6.6 Typical Characteristics

UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_1.gif
Figure 1. Supply Current vs Supply Voltage
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_3.gif
Figure 3. UVLO Thresholds vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_5.gif
Figure 5. Current Sense Input Threshold vs Multiplier Input Voltage
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_7.gif
Figure 7. CS To Output Delay Time vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_9.gif
Figure 9. gM Amplifier Output Current vs Output Sense Voltage
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_11.gif
Figure 11. Voltage Amplifier Output vs Time (UCC38050)
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_13.gif
Figure 13. Zero Current Detection Clamp Current vs Voltage
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_15.gif
Figure 15. Output Saturation Voltage vs Source Current
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_2.gif
Figure 2. Supply Current vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_4.gif
Figure 4. Reference Voltage vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_6.gif
Figure 6. Maximum Current Sense Threshold vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_8.gif
Figure 8. Transconductance vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_10.gif
Figure 10. gM Amplifier Output Current vs Output Sense Voltage (Small Signal View)
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_12.gif
Figure 12. Overvoltage Protection Thresholds vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_14.gif
Figure 14. Restart Time vs Temperature
UCC28050 UCC28051 UCC38050 UCC38051 slus515_typchar_16.gif
Figure 16. Output Saturation Voltage vs Sink Current

7 Detailed Description

7.1 Overview

The UCC38050 and UCC38051 are PFC controllers for low-to-medium power applications requiring compliance with IEC 1000-3-2 harmonic reduction. The controller is designed for a boost preregulator operating in transition mode (also referred to as boundary-conduction mode or critical conduction-mode operation). It features a transconductance voltage amplifier for feedback error processing, a simple multiplier for generating a current command proportional to the input voltage, a current-sense (PWM) comparator, PWM logic, and a totem-pole driver for driving an external FET.

The UCC38050 and UCC38051, while being pin-compatible with other industry controllers providing similar functionality, offer many feature enhancements and tighter specifications, leading to an overall reduction in system implementation cost. The system performance is enhanced by incorporation of a zero-power detect function, which allows the controller output to shut down at light load conditions without running into overvoltage. The device also features innovative slew rate enhancement circuits, which improve the large signal transient performance of the voltage error amplifier. The low start-up and operating currents of the device result in low power consumption and ease of start-up. Highly accurate internal bandgap reference leads to tight regulation of output voltage in normal and OVP conditions, resulting in higher system reliability. The enable comparator ensures that the controller is off if the feedback sense path is broken or if the input voltage is very low.

There are two key parameteric differences between UCC38050 and UCC38051. The UVLO turn-on threshold of UCC38050 is 15.8 V, while for UCC38051 it is 12.5 V. Secondly, the gM amplifier source current for UCC38050 is typically 1.3 mA, while for UCC38051 it is 300 μA. The higher UVLO turn-on threshold of the UCC38050 allows quicker and easier start-up with a smaller VCC capacitance, while the lower UVLO turn-on threshold of UCC38051 allows the operation of the PFC chip to be easily controlled by the downsteam PWM controller in two-stage power converters. The UCC38050 gM amplifier also provides a full 1.3-mA typical source current for faster start-up and improved transient response when output is low, either at start-up or during transient conditions. The UCC38051 scales this source current back down to 300-μA typical source current to gradually increase the error voltage, preventing a step increase in line currents at start-up, but still providing good transient response. The UCC38051 is suitable for multiple applications, including AC adapters, where a two-stage power conversion is needed. The UCC38050 is suitable for applications such as electronic ballasts, where there is no down-stream PWM conversion and the advantages of a smaller VCC capacitor and improved transient response can be realized.

7.2 Functional Block Diagram

UCC28050 UCC28051 UCC38050 UCC38051 block_lus515.gif

7.3 Feature Description

7.3.1 UVLO and Reference Block

This block generates a precision reference voltage used to obtain tightly controlled UVLO threshold. In addition to generating a 2.5-V reference for the non-inverting terminal of the gM amplifier, it generates the reference voltages for blocks such as OVP, enable, zero power, and multiplier. An internal rail of 7.5 V is also generated, to drive all the internal blocks.

7.3.2 Error Amplifier

The voltage error amplifier in UCC3805x is a transcoductance amplifier, with a typical transconductance value of 90 μS. A transconductance amplifier is advantageous in that the inverting input of the amplifier is solely determined by the external resistive-divider from the output voltage, and not the transient behavior of the amplifier itself. This allows the VO_SNS pin to be used for sensing overvoltage conditions.

The sink and source capability of the error amplifier is approximately 10 μA during normal operation of the amplifier. However, when the VO_SNS pin voltage is beyond the normal operating conditions (VO_SNS > 1.05 × VREF, VO_SNS < 0.88 × VREF), additional circuitry to enhance the slew-rate of the amplifier is activated. Enhanced slew-rate of the compensation capacitor results in a faster start-up and transient response. This prevents the output voltage from drifting too high or too low, which can happen if the compensation capacitor were to be slewed by the normal slewing current of 10 μA. When VO_SNS rises above the normal range, the enhanced sink current capability is in excess of 1 mA. When VO_SNS falls below the normal range, the UCC38050 can source more than 1 mA, and the UCC38051 sources approximately 300 μA. The limited source current in the UCC38051 helps to gradually increase the error voltage on the COMP pin preventing a step increase in line current. The actual rate of increase of VCOMP depends on the compensation network connected to the COMP pin.

7.3.3 Zero Current Detection and Re-Start Timer Blocks

When the boost inductor current becomes zero, the voltage at the power MOSFET drain end falls. This is indirectly sensed with a secondary winding connected to the ZCD pin. The internal active clamp circuitry prevents the voltage from going to a negative or a high positive value. The clamp has the sink and source capability of 10 mA. The resistor value in series with the secondary winding should be chosen to limit the ZCD current to less than 10 mA. The rising edge threshold of the ZCD comparator can be as high as 2 V. The auxiliary winding should be chosen such that the positive voltage (when the power MOSFET is off) at the ZCD pin is in excess of 2 V.

The restart timer attempts to set the gate drive high in case the gate drive remains off for more than 400 μs nominally. The minimum guaranteed time period of the timer is 200 μs. This translates to a minimum switching frequency of 5 kHz. In other words, the boost inductor value should be chosen for switching frequencies greater than 5 kHz.

7.3.4 Enable Block

The gate drive signal is held low if the voltage at the VO_SNS pin is less than the ENABLE threshold. This feature can disable the converter by pulling VO_SNS low. If the output feedback path is broken, VO_SNS is pulled to ground, and the output is disabled to protect the power stage.

7.3.5 Zero Power Block

When the output of the gM amplifier goes below 2.3 V, the zero power comparator latches the gate drive signal low. The slew rate enhancement circuitry of the gM amplifier activated during overvoltage conditions slews the COMP pin to approximately 2.4 V. This ensures that the zero power comparator is not activated during transient behavior, when the slew rate enhancement circuitry is enhanced.

7.3.6 Multiplier Block

The multiplier block has two inputs. One is the error amplifier output voltage (VCOMP), and the other is VMULTIN, which is obtained by a resistive divider from the rectified line. The multiplier output is approximately 0.67 × VMULTIN × (VCOMP − 2.5 V). There is a positive offset of about 75 mV to the VMULTIN signal because this improves the zero-crossing distortion and thus the THD performance of the controller in the application. The dynamic range of the inputs can be found in Electrical Characteristics.

7.3.7 Overvoltage Protection (OVP) Block

The OVP feature in the part is not activated under most operating conditions because of the presence of the slew rate enhancement circuitry present in the error amplifier. As soon as the output voltage reaches to approximately 5% to 7% above the nominal value, the slew rate enhancement circuit is activated, and the error amplifier output voltage is pulled below the dynamic range of the multiplier block. This prevents further rise in output voltage.

If the COMP pin is not pulled low fast enough and the voltage rises further, the OVP circuit acts as a second line of protection. When the voltage at the VO_SNS pin is more than 7.5% of the nominal value (> (VREF + 0.19)), the OVP feature is activated. It stops the gate drive from switching as long as the voltage at the VO_SNS pin is above the nominal value (VREF). This prevents the output DC voltage from going above 7.5% of the nominal value designed for, and protects the switch and other components of the system such as the boost capacitor.

7.4 Device Functional Modes

7.4.1 Transition Mode Control

The boost converter, the most common topology used for power factor correction, can operate in two modes: continuous conduction code (CCM) and discontinuous conduction mode (DCM). Transition mode control, also referred to as critical conduction mode (CRM) or boundary conduction mode, maintains the converter at the boundary between CCM and DCM by adjusting the switching frequency.

The CRM converter typically uses a variation of hysteretic control, with the lower boundary equal to zero current. It is a variable frequency control technique that has inherently stable input current control while eliminating reverse recovery rectifier losses. As shown in Figure 17, the switch current is compared to the reference signal (output of the multiplier) directly. This control method has the advantage of simple implementation and good power factor correction.

UCC28050 UCC28051 UCC38050 UCC38051 basic_bd_crm_boost_pfc.gif Figure 17. Basic Block Diagram of CRM Boost PFC

The power stage equations and the transfer functions of the CRM are the same as the CCM. However, implementations of the control functions are different. Transition mode forces the inductor current to operate just at the border of CCM and DCM. The current profile is also different, and affects the component power loss and filtering requirements. The peak current in the CRM boost is twice the amplitude of CCM, leading to higher conduction losses. The peak-to-peak ripple is twice the average current, which affects MOSFET switching losses and magnetics ac losses.

UCC28050 UCC28051 UCC38050 UCC38051 pfc_inductor_curr_prof.gif Figure 18. PFC Inductor Current Profiles

For low to medium power applications up to approximately 300 W, the CRM boost has an advantage in losses. The filtering requirement is not severe, and therefore is not a disadvantage. For medium to higher power applications, where the input filter requirements dominate the size of the magnetics, the CCM boost is a good choice due to lower peak currents (which reduces conduction losses) and lower ripple current (which reduces filter requirements). The main tradeoff in using CRM boost is lower losses due to no reverse recovery in the boost diode vs. higher ripple and peak currents.

 
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