JAJSM24A December 2023 – May 2024 ADC3910D025 , ADC3910D065 , ADC3910D125 , ADC3910S025 , ADC3910S065 , ADC3910S125
PRODUCTION DATA
In serial CMOS mode, the ADC3910Dx および ADC3910Sx has a configurable output data mapping. Default bit size in serial CMOS is 10 bits wide and interface default is set to DDR. Interface options are double data rate (DDR), half double data rate (HDDR), and single data rate (SDR) via SPI write to register 0x098.
By default DDR mode clocks output data by alternating channel A data on the rising and channel B data on the falling edge of DCLK on the same lane. This behavior can be changed to clock all of channel A data first and then channel B data via SPI write to DDR_MODE (0x0A6). HDDR mode clocks channel A data on separate output lanes from channel B data via SPI write to HDDR_EN (0x098).
SDR mode clocks data only on rising edge; therefore, to clock both data samples in a cycle, requires double the data clock speed. The following diagrams show the different available configurations that can be programmed, and Table 6-4 shows actual data and clock rates.
Output Resolution | Decimation | Lanes | Serialization | DCLK | DCLK Divider | FCLK |
---|---|---|---|---|---|---|
Register 0xA7 | Register 0x200 | Registers 0xAE...B3 | Register 0xA6 | Register 0xA8 | Register 0x88 | |
8 bits | Bypass | 8 | 1 | FS | /1 | N/A |
10 bits | 10 | 1 | FS | /1 | N/A | |
12 bits | 12 | 1 | FS | /1 | N/A | |
/2 | 12 | 1 | FS / 2 | /2 | N/A | |
/4 | 12 | 1 | FS / 4 | /4 | N/A | |
/8 | 12 | 1 | FS / 8 | /8 | N/A | |
/16 | 12 | 1 | FS /16 | /16 | N/A | |
16 bits | /2 | 8 | 2 | FS | /2 | FS / 2 |
/4 | 8 | 2 | FS / 2 | /4 | FS / 2 | |
4 | 4 | FS | FS / 4 | |||
/8 | 8 | 2 | FS / 4 | /8 | FS / 2 | |
4 | 4 | FS / 2 | FS / 4 | |||
2 | 8 | FS | FS / 8 | |||
/16 | 8 | 2 | FS / 8 | /16 | FS / 2 | |
4 | 4 | FS / 4 | FS / 4 | |||
2 | 8 | FS / 2 | FS / 8 |