JAJSM24A December 2023 – May 2024 ADC3910D025 , ADC3910D065 , ADC3910D125 , ADC3910S025 , ADC3910S065 , ADC3910S125
PRODUCTION DATA
Address | Register Name |
---|---|
1AFh | ALERT_PULSE_WIDTH |
1B4h | ALERT_INVERT_7:0 |
1B5h | ALERT_INVERT_15:8 |
1B6h | ALERT_INVERT_18:16 |
1C0h | ALERT_TRIG_7:0 |
1C1h | ALERT_TRIG_15:8 |
1C2h | ALERT_TRIG_18:16 |
1CCh | ALERT_STICKY_7:0 |
1CDh | ALERT_STICKY_15:8 |
1CEh | ALERT_STICKY_18:16 |
1D8h | ALERT_STICKY_CLR_7:0 |
1D9h | ALERT_STICKY_CLR_15:8 |
1DAh | ALERT_STICKY_CLR_18:16 |
1E4h | ALERT_CNT_7:0 |
1E5h | ALERT_CNT_15:8 |
1EAh | ALERT_CNT |
1ECh | ALERT_THRESHOLD_7:0 |
1EDh | ALERT_THRESHOLD_15:8 |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_PULSE_WIDTH | R/W | 0h | ALERT pulse width = 2ALERTPULSE WIDTH + 1 CLK cycles. Minimum width is 1 CLK cycle. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_INVERT__7:0 | R/W | 0h | Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. Bit 0: Equal to THRESHOLD HI CHA Bit 1: Greater than THRESHOLD HI CHA Bit 2: Less than THRESHOLD LO CHA Bit 3: All ones Bit 4: All zeros Bit 5: Less than THRESHOLD HI CHA Bit 6: Greater than THRESHOLD LO CHA Bit 7: Equal to THRESHOLD HI CHB Bit 8: Greater than THRESHOLD HI CHB Bit 9: Less than THRESHOLD LO CHB Bit 10: All ones Bit 11: All zeros Bit 12: Less than THRESHOLD HI CHB Bit 13: Greater than THRESHOLD LO CHB Bit 14: ADC channel A overrange Bit 15: ADC channel B overrange Bit 16: Statistics engine window complete |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_INVERT__15:8 | R/W | 0h | Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
2:0 | ALERT_INVERT__18:16 | R/W | 0h | Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_TRIG__7:0 | R/W | 0h | Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_TRIG__15:8 | R/W | 0h | Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
0 | ALERT_TRIG__18:16 | R/W | 0h | Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_STICKY__7:0 | R/W | 0h | Signals set as sticky for ALERT pin, that is, once triggered remains triggered until cleared in ALERT STICKY CLR MASK. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_STICKY__15:8 | R/W | 0h | Signals set as sticky for ALERT pin, that is, once triggered remains triggered until cleared in ALERT STICKY CLR MASK. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
0 | ALERT_STICKY__18:16 | R/W | 0h | Signals set as sticky for ALERT pin, that is, once triggered remains triggered until cleared in ALERT STICKY CLR MASK. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_STICKY_CLR__7:0 | R/W | 0h | Signals set as sticky for ALERT pin. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_STICKY_CLR__15:8 | R/W | 0h | Signals set as sticky for ALERT pin. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
0 | ALERT_STICKY_CLR__18:16 | R/W | 0h | Signals set as sticky for ALERT pin. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_CNT__7:0 | R/W | 0h | Counter of the input alerts cross the threshold before the output alert is triggered |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_CNT__15:8 | R/W | 0h | Counter of the input alerts cross the threshold before the output alert is triggered |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CNT_MODE_B | R/W | 0h | Sets the ALERT count mode for channel B 0b = Level-based count 1b = Rise-based count |
6 | CNT_MODE_A | R/W | 0h | Sets the ALERT count mode for channel A 0b = Level-based count 1b = Rise-based count |
5:1 | RESERVED | R | 0h | |
0 | CNT_EN | R/W | 0h | Enables alert window mode. In this mode alert is
triggered when input triggers cross (alert_thres) number of time in
alert_cnt window 0b = Disable alert window mode 1b = Enable alert window mode |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_THRESHOLD__7:0 | R/W | 0h | Sets the threshold the count of input alerts must cross before the output alert is triggered |
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | ALERT_THRESHOLD__15:8 | R/W | 0h | Sets the threshold the count of input alerts must cross before the output alert is triggered |