JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all specifications are at AVDD = DVDD = V(REFP) = 5 V, V(REFN) = AGND, and fCLK = 4.9152 MHz (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ANALOG INPUTS
Differential input currentGain = 1±3nA
Gain = 2±6
Gain = 64, 128±3.5
SYSTEM PERFORMANCE
ResolutionNo missing codes24Bits
fDATAData rateInternal oscillator, SPEED = high788082.4SPS
Internal oscillator, SPEED = low9.751010.3
External oscillator, SPEED = highfCLK / 61,440
External oscillator, SPEED = lowfCLK / 491,520
Digital filter settling timeFull settling, readings synchronized with A0, A1 pins4Conversions
INLIntegral nonlinearityDifferential input, end-point fit, gain = 1, 2–0.001±0.00020.001% of FSR(1)
Differential input, end-point fit, gain = 64, 128±0.0004
Input offset error(2)Gain = 1–5±0.25ppm of FS
Gain = 128–1±0.021
Input offset driftGain = 1±0.3µV/°C
Gain = 128±10nV/°C
Gain error(3)Gain = 1–0.02±0.0010.02%
Gain = 128–0.1±0.010.1
Gain driftGain = 1±0.2ppm/°C
Gain = 128±2.5
NMRRNormal-mode rejection ratio (4)Internal oscillator, fDATA = 10 SPS
fIN = 50 Hz or 60 Hz, ±1 Hz		100110dB
External oscillator, fDATA = 10 SPS
fIN = 50 Hz or 60 Hz, ±1 Hz		120130
CMRRCommon-mode rejection ratioAt DC, gain = 1, ΔV = 1 V, VCM = AVDD / 295110dB
At DC, gain = 128, ΔV = 0.1 V, VCM = AVDD / 295110
enInput-referred noiseSee the Section 7.1 section
PSRRPower-supply rejectionAVDD, at DC, gain = 1, ΔV = 1 V85dB
AVDD, at DC, gain = 128, ΔV = 0.1 V100120
VOLTAGE REFERENCE INPUT
Input current10nA
DIGITAL LOGIC LEVELS
VIHHigh-level input voltage0.7 DVDDV
VILLow-level input voltage0.2 DVDDV
VOHHigh-level output voltageIOH = 1 mADVDD – 0.4V
VOLLow-level output voltageIOL = 1 mA0.2 DVDDV
Input leakage current0 V < VIN < DVDD–1010µA
POWER SUPPLY
I(AVDD)Analog supply currentNormal mode, AVDD = 3 V, gain = 1, 26001300µA
Normal mode, AVDD = 3 V, gain = 64, 12813502500
Normal mode, AVDD = 5 V, gain = 1, 26501300
Normal mode, AVDD = 5 V, gain = 64, 12813502500
Standby mode0.11
Power-down0.11
I(DVDD)Digital supply currentNormal mode, DVDD = 3 V, gain = 1, 26095µA
Normal mode, DVDD = 3 V, gain = 64, 12875120
Normal mode, DVDD = 5 V, gain = 1, 295130
Normal mode, DVDD = 5 V, gain = 64, 12875120
Standby mode, SCLK = high, DVDD = 3 V4580
Standby mode, SCLK = high, DVDD = 5 V6580
Power-down0.21.3
PDPower dissipation, totalNormal mode, AVDD = DVDD = 3 V, gain = 1, 224.2mW
Normal mode, AVDD = DVDD = 5 V, gain = 1, 23.77.2
Normal mode, AVDD = DVDD = 3 V, gain = 64, 1284.37.9
Normal mode, AVDD = DVDD = 5 V, gain = 64, 1287.113.1
Standby mode, AVDD = DVDD = 5 V0.30.4
(1) FSR = full-scale range = VREF / Gain.
(2) Input offset error specified after calibration. Recalibration minimizes these errors to the level of noise at any temperature.
(3) Gain errors are calibrated at the factory (AVDD = 5 V, all gains, TA = 25°C).
(4) Specification is assured by the combination of design and final production test.