JAJSOX0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
Individual channels are powered down by the PWDNn control bits of the respective CHn_CFG2 channel configuration registers. The analog and digital sections of the channel are disabled and the output data are the last known data. In TDM mode, the slot position within the data frame is the same as when the channel is active. When a channel is programmed to be active, all channels reset the time of SPI register write. Resynchronize the ADC if required. If activating at least one channel from an all-channel power-down, wait 300µs before synchronizing the channels.