JAJSOX0B March 2024 – November 2024 ADS127L18
PRODMIX
Channels are individually powered down by the CHn_PWDN bits of the respective CHn_CFG2 configuration registers. The analog section of the channel is disabled and the output data are the last known data. In TDM mode, the slot position of a powered down channel is retained. When a channel is re-enabled, the conversions reset at the time of SPI register write. Resynchronize the ADC if required. If activating channels from all-channel power down, wait 300µs before synchronizing the channels.