JAJSOX0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
To help detect SPI errors, an SPI clock counter is available. When enabled, the required number of SCLK clock cycles within an SPI frame is a multiple of 8. The SCLK_ERR bit of the STATUS register sets if the number of SCLK cycles is not a multiple of 8. Except for the STATUS register, register write operations are blocked until the flag is cleared by writing 1b to the bit. The SCLK count feature is enabled by setting SCLK_CNT_EN = 1 of the GEN_CFG3 register.