JAJSOX0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
The ADC provides a clock counter to verify the clock frequency. To verify the clock frequency, read the CLK_CNT clock counter register at known intervals. Then compare the register value to the expected value based on the ensuing number of clock cycles. The ADS127L1x must be in conversion mode and a minimum SCLK frequency of CLK / 32 to is required to read the counter value.
The clock counter operates in rollover mode with the input frequency of ADC clock / 32. The counter is enabled by the CLK_CNT_EN bit of the GEN_CFG3 register. When enabled, the counter value initializes to 00h. When disabled, the counter value is 00h.