JAJSOX0A March   2024  – June 2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUT Pins
        4. 7.4.11.4 DIN Pins
        5. 7.4.11.5 Time Division Multiplexing
        6. 7.4.11.6 Daisy Chain
        7. 7.4.11.7 Data Packet
        8. 7.4.11.8 STATUS_DP Header
        9. 7.4.11.9 Data Port Timing Adjustment
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. Register Map
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Analog Inputs (AINP, AINN)

The analog inputs of each ADC channel are differential, with the input defined as a difference voltage: VIN = ±(VAINP – VAINN). For best performance, drive the input with a differential signal with the common-mode voltage centered to mid-supply (AVDD1 + AVSS) / 2.

The ADC accepts either unipolar or bipolar input signals by configuring AVDD1 and AVSS accordingly. Figure 7-1 illustrates an example of a differential signal in unipolar supply configuration. Symmetric input voltage headroom is provided when the common-mode voltage is at mid-supply (AVDD1 / 2). For unipolar operation, use AVDD1 = 5V and AVSS = 0V (mid- and low-speed modes offer the option of reduced AVDD1 supply voltage). The VCM pin provides a buffered common-mode voltage to level-shift the signal voltage in the external driver stage.

Figure 7-2 illustrates an example of a differential signal in bipolar supply configuration. The common-mode voltage of the signal is normally = 0V. For bipolar operation, use AVDD1 and AVSS = ±2.5V (mid- and low-speed modes offer the option of reduced AVDD1 – AVSS supply voltage).

ADS127L14 ADS127L18 Unipolar Differential
                        Input SignalFigure 7-1 Unipolar Differential Input Signal
ADS127L14 ADS127L18 Bipolar Differential Input
                        SignalFigure 7-2 Bipolar Differential Input Signal

In both bipolar and unipolar configurations, the ADC accepts single-ended input signals by tying the AINN input to AVSS, ground, or to mid-supply. However, because AINN is a fixed voltage, the full differential input swing range is lost. Thus, the ADC dynamic range is limited to the voltage swing of the AINP input (±2.5V or 0V to 5V for a 5V supply).

The circuit of Figure 7-3 shows the simplified analog input circuit of each ADC channel. Diodes protect the ADC inputs from electrostatic discharge (ESD) events that occur during the manufacturing process and during printed circuit board (PCB) assembly when manufactured in an ESD-controlled environment. If the inputs are driven below AVSS – 0.3 V, or above AVDD1 + 0.3 V, the protection diodes potentially conduct. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the input current to the specified value.

ADS127L14 ADS127L18 Analog Input Circuit Figure 7-3 Analog Input Circuit

The input multiplexers of each ADC channel are independently configurable. The multiplexer offers the option of normal or reverse input signal polarities. The multiplexer test modes help verify ADC performance and provide diagnostic tests. The offset test mode verifies noise and offset errors by shorting the internal inputs to the mid-supply voltage. The resulting noise and offset voltage data are evaluated by the user. The full-scale input of each ADC channel is tested for gain error by selecting the –VREF or VREF internal connection. The VREF test signals are at the ADC full-scale signal range. Thus, reduce the value of the digital gain scale registers or program the extended range mode to avoid clipped output codes. The CMRR test mode verifies CMRR performance by applying a dc or ac test signal to the AINP or AINN inputs. The resulting CMRR test data are evaluated by the user.

Table 7-1 shows the switch configurations of the input multiplexer circuit of Figure 7-3.

Table 7-1 Input Multiplexer Configurations
CHn_MUX[2:0] BITS SWITCHES DESCRIPTION
000b S1, S4 Normal polarity input
001b S2, S3 Reverse polarity input
010b S9, S10 Input short for offset voltage and noise test
011b S1, S10 Input short using a signal applied to AINPn for CMRR test
100b S4, S10 Input short using a signal applied to AINNn for CMRR test
101b S6, S7 –FS dc signal for gain test
110b S5, S8 +FS dc signal for gain test
111b S5, S8 +FS dc signal for gain test

The input sampling capacitor CIN is part of the simplified input sampling network denoted by the dashed box in Figure 7-3. The instantaneous charge demand of CIN requires the signal to settle within a half cycle at the modulator frequency t = 1 / (2 · fMOD). To satisfy this requirement, the driver bandwidth is typically much larger than the original signal frequency. The bandwidth of the driver is determined as sufficient when the THD and SNR data sheet performance are achieved. Because the modulator sampling rate is eight times slower in low-speed mode compared to high-speed mode, more time is available for driver settling.

The charge required by the input sampling capacitor is modeled as an average input current of the ADC inputs. As shown in Equation 22 and Equation 16, the input current is comprised of differential and absolute components.

Equation 15. Input Current (Differential Input Voltage) = fMOD · CIN · 106 (μA/V)

where:

  • fMOD = fCLK / 2
  • CIN = 7.4pF (1x input range), 3.6pF (2x input range)

Equation 16. Input Current (Absolute Input Voltage) = fMOD · CCM · 106 (μA/V)

where:

  • fMOD = fCLK / 2
  • CCM = 0.35pF (1x input range), 0.17pF (2x input range)

For fMOD = 12.8MHz (high-speed mode), CIN = 7.4pF and CCM = 0.3pF. The input current resulting from the differential voltage is 95μA/V and the input current resulting from the absolute voltage is 4.5μA/V. For example, if AINPn = 4.5V and AINNn = 0.5 , then VIN = 4V. The total AINPn input current = (4V · 95μA/V) + (4.5V · 4.5μA/V) = 400μA. The total AINNn current is (–4V · 95μA/V) + (0.5 · 4.5μA/V) = –378μA.

The device incorporates input precharge buffers to significantly reduce the charge required by capacitor CIN. In operation, near the end of the sampling phase, capacitor CIN is nearly fully charged by the precharge buffers. The buffers are disconnected (S11 and S12 of Figure 7-3 in up positions) to allow the external driver to provide the fine charge to the capacitor. When the sample phase is completed, the sampling capacitor is discharged to complete the cycle, at which time the sample process repeats. The operation of the precharge buffers reduces the input current by 99%, and in many cases leads to improved THD and SNR performance. The precharge buffers are enabled by the CHn_BUFP and CHn_BUFN bits of the CHn_CFG1 register. If the AINN input of any channel is tied to ground or to a low-impedance source, disable the AINN buffer to reduce power consumption. A single-ended input application is an example of a low-impedance source.