JAJSPW8E march   2011  – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions – LVDS Mode
    2.     Pin Functions – CMOS Mode
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 7.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes #GUID-C6C0701B-A11B-492F-BD6B-B774F5FE4665/SLAS6895399
    10. 7.10 Serial Interface Timing Characteristics #GUID-3852E7CE-C5B6-42F5-A56A-70AB1B981302/SBAS5097810
    11. 7.11 Reset Timing (Only When Serial Interface Is Used)
    12. 7.12 Typical Characteristics
      1. 7.12.1 ADS4246
      2. 7.12.2 ADS4245
      3. 7.12.3 ADS4242
      4. 7.12.4 ADS4226
      5. 7.12.5 ADS4225
      6. 7.12.6 ADS4222
      7. 7.12.7 General
      8. 7.12.8 Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Drive Circuit Requirements
        2. 8.3.1.2 Driving Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 Digital Functions
      4. 8.3.4 Gain for SFDR/SNR Trade-off
      5. 8.3.5 Offset Correction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down
        1. 8.4.1.1 Global Power-Down
        2. 8.4.1.2 Channel Standby
        3. 8.4.1.3 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 47
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
      7. 8.5.7 Digital Output Information
        1. 8.5.7.1 Output Interface
        2. 8.5.7.2 DDR LVDS Outputs
        3. 8.5.7.3 LVDS Buffer
        4. 8.5.7.4 Parallel CMOS Interface
        5. 8.5.7.5 CMOS Interface Power Dissipation
        6. 8.5.7.6 Multiplexed Mode of Operation
        7. 8.5.7.7 Output Data Format
    6. 8.6 Register Maps
      1. 8.6.1 64
      2. 8.6.2 Description Of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
        4. 9.2.2.4 SNR and Clock Jitter
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Sharing DRVDD and AVDD Supplies
      2. 9.3.2 Using DC/DC Power Supplies
      3. 9.3.3 Power Supply Bypassing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Grounding
        2. 9.4.1.2 Supply Decoupling
        3. 9.4.1.3 Exposed Pad
        4. 9.4.1.4 Routing Analog Inputs
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from Revision D (December 2015) to Revision E (February 2023)

  • 「デバイス情報」表を「パッケージ情報」表に変更Go
  • 「パッケージ情報」表の VQFN (48) を VQFN (64) に変更Go
  • Changed the Pin Configuration and Functions. Updated the Pin Functions tables and pinout imagesGo

Changes from Revision C (March 2011) to Revision D (December 2015)

  • 「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加。Go

Changes from Revision B (May 2011) to Revision C (March 2011)

  • ドキュメントのステータスを「混合ステータス」から「量産データ」に変更Go
  • 「特長」の最初の箇条書き項目の 125MSPS の副項目を変更Go
  • 「特長」の 2 番目の箇条書きの副項目を変更Go
  • Changed description of pin 64 in Pin Descriptions: LVDS Mode tableGo
  • Changed description of pin 64 in Pin Descriptions: CMOS Mode tableGo
  • Changed ADS4246 fIN = 170 MHz Worst spur typical spcification in the ADS4246/ADS4245/ADS4242 Electrical Characteristics tableGo
  • Added ADS4225/ADS4222 fIN = 70 MHz SNR, SINAD, SFDR, THD, HD2, HD3, and Worst spur minimum and typical spcifications in the ADS4226/ADS4225/ADS4222 Electrical Characteristics tableGo
  • Added ADS4225/ADS4222 DNL minimum and maximum spcifications in the ADS4226/ADS4225/ADS4222 Electrical Characteristics tableGo
  • Added ADS4225/ADS4222 INL maximum spcifications in the ADS4226/ADS4225/ADS4222 Electrical Characteristics tableGo
  • Changed ADS4242/ADS4222 Power Supply, Digital power LVDS interface typical specification in Electrical Characteristics: General tableGo
  • Changed ADS4245/ADS4225 Power Supply, Digital power CMOS interface typical specification in Electrical Characteristics: General tableGo
  • Moved High-Performance Modes into separate tableGo
  • Changed description of READOUT disabled in Serial Register Readout sectionGo
  • Updated Figure 8-18 Go
  • Changed READOUT desciption in Register Address 00h sectionGo
  • Changed CLKOUT FALL POSN and CLKOUT RISE POSN description in Register Address 42h sectionGo

Changes from Revision A (May 2011) to Revision B (May 2011)

  • 「特長」の最初の箇条書き項目の副項目を変更Go
  • Updated description of NC pin in LVDS Pin Descriptions tableGo
  • Updated description of NC pin in CMOS Pin Descriptions tableGo
  • Changed ENOB, DNL, and INL test conditions in the Electrical Characteristics: ADS4246/ADS4245/ADS4242 table Go
  • Deleted INL minimum specifications from Electrical Characteristics: ADS4246/ADS4245/ADS4242 tableGo
  • Changed INL maximum specifications in the Electrical Characteristics: ADS4246/ADS4245/ADS4242 tableGo
  • Changed ENOB, DNL, and INL test conditions in the Electrical Characteristics: ADS4226/ADS4225/ADS4222 table Go
  • Changed ADS4226 INL maximum specification in the Electrical Characteristics: ADS4226/ADS4225/ADS4222 tableGo
  • Changed Power Supply, IDRVDD and Digital power CMOS interface rows in the Electrical Characteristics: General tableGo
  • Updated Figure 7-16 Go
  • Updated Figure 7-18 Go
  • Updated Figure 7-37 and Figure 7-38 Go
  • Updated Figure 7-39 and Figure 7-40 Go
  • Updated Figure 7-58 and Figure 7-59 Go
  • Updated Figure 7-60 and Figure 7-61 Go
  • Updated Figure 7-79 and Figure 7-80 Go
  • Updated Figure 7-81 and Figure 7-82 Go
  • Updated Figure 7-96 Go
  • Updated Figure 7-97 and SBAS533graph8650Go
  • Updated Figure 7-115 Go
  • Updated Figure 7-127 Go
  • Changed title of Figure 7-128 Go
  • Updated ADS424x/422x Family Pins section in Table 8-1 Go
  • Changed 111110 and 001111 LVDS SWING description in Register Address 01hGo