9.2.3 Application Curves

This section outlines the trends described in the Typical Characteristics section from an application perspective.

Figure 2 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 3 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 100 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 4 illustrates the FFT with a 5-MHz input signal for 8-input mode with the ADC resolution set to 10 bits. The system clock provided is 200 MSPS and the input is sampled at an effective rate of 200 MSPS, which is the maximum sampling rate for this mode of operation. The increase in sampling rate is achieved through two ADCs converting the same input in an interleaved manner. The interleaving spurs are visible in the FFT. The predominant spur is at the frequencies of (f_S / 2 ± f_IN), which appear at 95 MHz. Additional spurs are at the frequencies of (f_S / 4 ± f_IN), which appear at 45 MHz and 55 MHz. The magnitude of the spurs is expected to rise when the input frequency is increased. Also, the spur level is sensitive to the matching of the manner in which the two sets of input pins are driven. A spur at f_S/4 is also seen. This arises from the offset mismatch between the four sets of sampling circuits used to sample the same input.

Figure 5 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 40 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 6 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 80 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 7 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 32.5 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 8 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 65 MSPS, which is the maximum sampling rate for this mode of operation. In addition to the harmonics, the spur at the frequency (f_S / 2 ± f_IN) also occurs at 27.5 MHz. This spur is caused by the interleaved sampling of the input signal by two physically different sampling circuits of the same ADC.

Figure 9 illustrates the signal-to-noise ratio (SNR) versus the frequency of the input signal for 32-input mode with the ADC resolution set to 10 bits. SNR is expressed in the dBFS scale where the RMS noise at the ADC output is referred to the full-scale differential voltage of 2 V. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. SNR is computed by integrating the noise in all FFT bins after excluding the first nine harmonics. SNR is dominated by the quantization noise of the 10-bit conversion.

Figure 10 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 100 MSPS. SNR is computed by integrating the noise in all FFT bins after excluding the first nine harmonics and any interleaving spurs. SNR is dominated by the quantization noise of the 10-bit conversion.

Figure 11 illustrates SNR versus the frequency of the input signal for 8-input mode with the ADC resolution set to 10 bits. The system clock provided is 200 MSPS and the input is sampled at an effective rate of 200 MSPS. SNR is computed by integrating the noise in all FFT bins after excluding the first nine harmonics and any interleaving spurs at (f_S / 2 ± f_IN) and (f_S / 4 ± f_IN) as well as additional spurs at f_S / 2 and f_S / 4. SNR is dominated by the quantization noise of the 10-bit conversion.

Figure 12 illustrates SNR versus the frequency of the input signal for 32-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 40 MSPS.

Figure 13 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 80 MSPS.

Figure 14 illustrates SNR versus the frequency of the input signal for 32-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 32.5 MSPS. SNR at high input frequencies degrades because of clock jitter.

Figure 15 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 65 MSPS.

Figure 16 illustrates the amplitude of the third-order harmonic distortion (HD3) of the input signal versus the frequency of the input signal. The unit of dBc indicates that the HD3 amplitude is referred to the amplitude of the input signal, which is set to –1 dBFS. Figure 16 is taken for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows a similar trend across the other input modes and resolutions.

Figure 17 illustrates the amplitude of the second-order harmonic distortion (HD2) of the input signal versus the frequency of the input signal. The unit of dBc indicates that the HD2 amplitude is referred to the amplitude of the input signal, which is set to –1 dBFS. Figure 17 is taken for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows a similar trend across the other input modes and resolutions.

Figure 18 illustrates the total harmonic distortion (THD) versus the frequency of the input signal. The THD parameter includes the RMS amplitude of the first nine harmonics of the fundamental signal. The unit of dBc indicates that THD is referred to the amplitude of the input signal, which is set to –1 dBFS. Figure 18 is taken for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows a similar trend across the other input modes and resolutions.

Figure 19 illustrates the interleaving spur at (f_S / 2 ± f_IN) versus the frequency of the input signal. Figure 19 is taken for 8-input mode with the ADC resolution set to 10 bits. The system clock is set to 200 MSPS and the input is sampled at an effective rate of 200 MSPS. The interleaving spur at (f_S / 2 ± f_IN) is referred to the fundamental amplitude, which is at a level of –1 dBFS. The (f_S / 2 ± f_IN) spur comes about because of the interleaved conversion of the same input by two ADCs. As illustrated in Figure 19, the interleaving spur gets much worse at higher input frequencies. This degradation results from the fact that when the input frequency is increased, any mismatch in the sampling bandwidths and sampling instants of the two interleaved ADCs leads to a larger phase error between the interleaved conversions.

Figure 20 illustrates the interleaving spur at (f_S / 2 ± f_IN) versus the frequency of the input signal. Figure 20 is taken for 16-input mode with the ADC resolution set to 10 bits. The system clock is set to 100 MSPS and the input is sampled at an effective rate of 100 MSPS. The (f_S / 2 ± f_IN) spur comes about because of the interleaved sampling of the input by the two sampling circuits of one ADC. Although not as bad as the (f_S / 2 ± f_IN) spur for 8-input mode, the interleaving spur could still be the dominant factor governing the SFDR at high input frequencies.

Figure 21 illustrates the interleaving spur at (f_S / 4 ± f_IN) versus the frequency of the input signal. Figure 21 is taken for 8-input mode with the ADC resolution set to 10 bits. The system clock is set to 200 MSPS and the input is sampled at an effective rate of 200 MSPS. In 8-input mode, there are a total of four sampling circuits (two in each ADC) that sample the same input in sequence. The (f_S / 4 ± f_IN) spur comes about from mismatches between these four sampling circuits.

Figure 22 illustrates SNR in dBFS as a function of the input amplitude, also expressed in dBFS. SNR excludes the first nine harmonics and the interleaving spurs. Figure 22 is taken for the 16-input mode with the ADC resolution set to 14 bits. The system clock is set to 65 MSPS and the input is sampled at an effective rate of 65 MSPS. The points in the left extreme of the curve provide an estimate of the idle channel SNR (SNR in the absence of an input signal).

Figure 23 illustrates the spurious-free dynamic range (SFDR) as a function of the input amplitude. Figure 23 is taken for 32-input mode with the ADC resolution set to 14 bits. In 32-input mode, there is no interleaved operation of any sort and SFDR is a true measure of ADC conversion performance. As mentioned previously, SFDR may be dominated by interleaving spurs (and significantly lower than 32-input mode) when operated in 16-input or 8-input modes. SFDR is plotted in both dBc and dBFS: the former referring the amplitude of the worst-spur to the fundamental amplitude and the latter to the full-scale voltage.

Figure 24 illustrates SNR as a function of the input common-mode voltage (average of INP and INM). Figure 24 is taken for 16-input mode with the ADC resolution set to 14 bits. The device is meant to be operated at an input common-mode that is tightly controlled around the ideal value of 0.8 V. The driving circuit can generate its output common-mode using the 0.8-V reference voltage provided at the VCM pin.

Figure 25 illustrates SNR as a function of the input clock amplitude (expressed in differential V_PP) when driven with a differential sine-wave clock input. At small input amplitudes, the sine-wave clock has a low dV/dt slope at the zero crossings. This low slope can cause increased jitter in the clocking and can lead to a reduction in the SNR within the device. The effect is more pronounced when the input frequency is set to a higher value (as is evidenced by the difference in behavior between the 5-MHz and 50-MHz inputs). The recommended manner to drive the device is with an LVPECL clock.

Figure 26 illustrates SNR as a function of the duty cycle of a differential clock input. Ideally, the device is driven with a 50% clock; see the Electrical Characteristics table for the acceptable variation around 50% duty cycle.

Figure 27 illustrates the channel-to-channel crosstalk as a function of the analog input frequency. An analog input of a –1-dBFS amplitude is applied on one channel and the crosstalk spur (at the input frequency) is measured on all channels. The worst of the crosstalk numbers (usually on the physically closest channel) is plotted.

Figure 28 illustrates the integral nonlinearity (INL) versus ADC code. The device is operated in 32-input mode at 14-bit resolution with an effective sampling rate of 32.5 MSPS. Figure 28 provides an accurate INL estimate of the ADC inside the device because there is no interleaving of any kind in the 32-input mode operation.

Figure 29 illustrates the differential nonlinearity (DNL) versus ADC code. The device is operated in 32-input mode at 14-bit resolution with an effective sampling rate of 32.5 MSPS. The saturation of the DNL on the lower side to –1 indicates missing codes at the 14-bit level.

Figure 30 illustrates the power-supply rejection ratio (PSRR) as a function of the tone frequency applied on the supply. A tone is applied on the supplies and the tone at the same frequency is measured at the device output. The unit of dBc refers to the relation of the amplitude of the output tone to the amplitude of the supply tone that is set to 100 mV_PP for this measurement.

Figure 31 illustrates the power-supply modulation ratio (PSMR) as a function of the tone frequency applied on the supply. A –1-dBFS input at 5 MHz is applied on the analog input. Simultaneously, a 100-mV_PP tone is applied on the supply. The tone caused by the intermodulation between the supply tone and the input tone is measured at the device output. PSMR refers to the intermodulation tone referred to in terms of dBc to the amplitude of the input tone.

Figure 32 illustrates the common-mode rejection ratio (CMRR) as a function of the tone frequency applied as a common-mode signal on the input pins. A 50-mV_PP common-mode signal is applied to INP and INM around the ideal common-mode voltage of 0.8 V. The amplitude of the tone at the same frequency is measured at the device output. CMRR refers to the amplitude of this output tone referred to in terms of dBc to the amplitude of the common-mode input tone.

Figure 33 illustrates the current of the AVDD_1P8 supply as a function of f_C, the conversion clock frequency. The relation of the sampling rate to the conversion clock frequency is different between the 16-, 32-, and 8- input modes and therefore the curve can be appropriately interpreted for each mode. The curve extends to a conversion clock frequency of up to 100 MSPS, which is the maximum value for the 10-bit ADC resolution. For the 12- and 14-bit ADC resolutions, sections of the same curve up to 80 MSPS and 65 MSPS (respectively) are applicable.

Figure 34 illustrates the current of the DVDD_1P8 supply as a function of the conversion clock frequency. All 16 LVDS buffers are on during this measurement.

Figure 35 illustrates the current of the DVDD_1P2 supply as a function of the conversion clock frequency.

Figure 36 illustrates the total power consumption as a function of the conversion clock frequency. The power per input channel can be calculated by dividing this total power by 8, 16, or 32 for the 8-, 16-, or 32-input modes.

Figure 37 illustrates the digital high-pass filter response for different settings of the HPF corner frequency.

Figure 38 illustrates the typical minimum and maximum SNR values taken across 100 devices operating in the 14-bit, 32-input mode at f_C = 65 MSPS (corresponding to f_SAMP = 32.5 MSPS). A trend can be observed across channels and originates from the physical placement and routing of common signals (such as reference voltage and power) to the channels. Depending on the way the channel data are combined, an averaging effect can result when the system-level SNR is computed.

Figure 39 illustrates a plot of the low-frequency noise from the device with and without the chopper enabled. When the chopper is enabled (using the CHOPPER_EN register control), the low-frequency noise generated inside the device is shifted to approximately f_S / 2. Chopper mode is useful when the signal frequency of interest is close to dc.

Figure 48 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-input mode operating with a 10-bit ADC resolution.

Figure 49 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-input mode operating with a 10-bit ADC resolution.

Figure 50 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 8-input mode operating with a 10-bit ADC resolution.

Figure 51 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-input mode operating with a 12-bit ADC resolution.

Figure 52 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-input mode operating with a 12-bit ADC resolution.

Figure 53 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-input mode operating with a 14-bit ADC resolution.

Figure 54 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-input mode operating with a 14-bit ADC resolution.