JAJSP50A May 2023 – September 2023 AMC131M03-Q1
PRODUCTION DATA
PIN | TYPE | DESCRIPTION(1) | |||
---|---|---|---|---|---|
NO. | NAME | ||||
1 | DCDC_OUT | Supply | High-side output of the DC/DC converter. Connect this pin to the HLDO_IN pin.(2) | ||
2 | DCDC_HGND | Supply | High-side ground reference for the DC/DC converter. Connect this pin to the HGND pin.(2) | ||
3 | HLDO_IN | Supply | Input of the high-side low-dropout (LDO) regulator. Connect this pin to the DCDC_OUT pin.(2) | ||
4 | HLDO_OUT | Supply | Output of the high-side LDO.(2) | ||
5 | HGND | Supply | High-side analog signal ground. Connect this pin to the DCDC_HGND pin. | ||
6 | AIN2P/GPO | Analog input | Positive analog input 2, or general-purpose output. | ||
7 | AIN12N | Analog input | Negative analog input 1 and 2. | ||
8 | AIN1P | Analog input | Positive analog input 1. | ||
9 | AIN0P(3) | Analog input | Positive analog input 0. | ||
10 | AIN0N(3) | Analog input | Negative analog input 0. | ||
11 | SYNC/RESET | Digital input | Conversion synchronization or system reset; active low. | ||
12 | DOUT | Digital output | Serial data output. | ||
13 | DVDD | Supply | Low-side analog and digital power supply.(2) | ||
14 | DCDC_CAP | Supply | Low-side input of the DC/DC converter, internally connected to the output of the primary-side LDO.(2) | ||
15 | DGND | Supply | Low-side analog and digital ground.(2) | ||
16 | DRDY | Digital output | Data ready; active low. | ||
17 | CLKIN | Digital input | Main clock input. | ||
18 | SCLK | Digital input | Serial data clock. | ||
19 | CS | Digital input | Chip select; active low. | ||
20 | DIN | Digital input | Serial data input. |