JAJSD77A
May 2017 – May 2018
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
アプリケーション図
4
改訂履歴
5
概要（続き）
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Power-Up from Battery Without DC Source
8.3.2
Power-Up From DC Source
8.3.2.1
CHRG_OK Indicator
8.3.2.2
Input Voltage and Current Limit Setup
8.3.2.3
Battery Cell Configuration
8.3.2.4
Device Hi-Z State
8.3.3
USB On-The-Go (OTG)
8.3.4
Converter Operation
8.3.4.1
Inductor Setting through IADPT Pin
8.3.4.2
Continuous Conduction Mode (CCM)
8.3.4.3
Pulse Frequency Modulation (PFM)
8.3.5
Current and Power Monitor
8.3.5.1
High-Accuracy Current Sense Amplifier (IADPT and IBAT)
8.3.5.2
High-Accuracy Power Sense Amplifier (PSYS)
8.3.6
Input Source Dynamic Power Manage
8.3.7
Two-Level Adapter Current Limit (Peak Power Mode)
8.3.8
Processor Hot Indication
8.3.8.1
PROCHOT During Low Power Mode
8.3.8.2
PROCHOT Status
8.3.9
Device Protection
8.3.9.1
Watchdog Timer
8.3.9.2
Input Overvoltage Protection (ACOV)
8.3.9.3
Input Overcurrent Protection (ACOC)
8.3.9.4
System Overvoltage Protection (SYSOVP)
8.3.9.5
Battery Overvoltage Protection (BATOVP)
8.3.9.6
Battery Short
8.3.9.7
Thermal Shutdown (TSHUT)
8.4
Device Functional Modes
8.4.1
Forward Mode
8.4.1.1
System Voltage Regulation with Narrow VDC Architecture
8.4.1.2
Battery Charging
8.4.2
USB On-The-Go
8.5
Programming
8.5.1
SMBus Interface
8.5.1.1
SMBus Write-Word and Read-Word Protocols
8.5.1.2
Timing Diagrams
8.6
Register Map
8.6.1
Setting Charge and PROCHOT Options
8.6.1.1
ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
Table 7.
ChargeOption0 Register (SMBus address = 12h) Field Descriptions
Table 8.
ChargeOption0 Register (SMBus address = 12h) Field Descriptions
8.6.1.2
ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
Table 9.
ChargeOption1 Register (SMBus address = 30h) Field Descriptions
Table 10.
ChargeOption1 Register (SMBus address = 30h) Field Descriptions
8.6.1.3
ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
Table 11.
ChargeOption2 Register (SMBus address = 31h) Field Descriptions
Table 12.
ChargeOption2 Register (SMBus address = 31h) Field Descriptions
8.6.1.4
ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
Table 13.
ChargeOption3 Register (SMBus address = 32h) Field Descriptions
Table 14.
ChargeOption3 Register (SMBus address = 32h) Field Descriptions
8.6.1.5
ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
Table 15.
ProchotOption0 Register (SMBus address = 33h) Field Descriptions
Table 16.
ProchotOption0 Register (SMBus address = 33h) Field Descriptions
8.6.1.6
ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
Table 17.
ProchotOption1 Register (SMBus address = 34h) Field Descriptions
Table 18.
ProchotOption1 Register (SMBus address = 34h) Field Descriptions
8.6.1.7
ADCOption Register (SMBus address = 35h) [reset = 2000h]
Table 19.
ADCOption Register (SMBus address = 35h) Field Descriptions
Table 20.
ADCOption Register (SMBus address = 35h) Field Descriptions
8.6.2
Charge and PROCHOT Status
8.6.2.1
ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
Table 21.
ChargerStatus Register (SMBus address = 20h) Field Descriptions
Table 22.
ChargerStatus Register (SMBus address = 20h) Field Descriptions
8.6.2.2
ProchotStatus Register (SMBus address = 21h) [reset = 0h]
Table 23.
ProchotStatus Register (SMBus address = 21h) Field Descriptions
Table 24.
ProchotStatus Register (SMBus address = 21h) Field Descriptions
8.6.3
ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
Table 25.
Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions
Table 26.
Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions
8.6.3.1
Battery Pre-Charge Current Clamp
8.6.4
MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
Table 27.
MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions
Table 28.
MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions
8.6.5
MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
Table 29.
MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions
Table 30.
MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions
8.6.5.1
System Voltage Regulation
8.6.6
Input Current and Input Voltage Registers for Dynamic Power Management
8.6.6.1
Input Current Registers
8.6.6.1.1
IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
Table 31.
IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
Table 32.
IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
8.6.6.1.2
IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
Table 33.
IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions
Table 34.
IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions
8.6.6.1.3
InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
Table 35.
InputVoltage Register (SMBus address = 3Dh) Field Descriptions
Table 36.
InputVoltage Register (SMBus address = 3Dh) Field Descriptions
8.6.7
OTGVoltage Register (SMBus address = 3Bh) [reset = 0h]
Table 37.
OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
Table 38.
OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
8.6.8
OTGCurrent Register (SMBus address = 3Ch) [reset = 0h]
Table 39.
OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
Table 40.
OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
8.6.9
ADCVBUS/PSYS Register (SMBus address = 23h)
Table 41.
ADCVBUS/PSYS Register Field Descriptions
8.6.10
ADCIBAT Register (SMBus address = 24h)
Table 42.
ADCIBAT Register Field Descriptions
8.6.11
ADCIINCMPIN Register (SMBus address = 25h)
Table 43.
ADCIINCMPIN Register Field Descriptions
8.6.12
ADCVSYSVBAT Register (SMBus address = 26h)
Table 44.
ADCVSYSVBAT Register Field Descriptions
8.6.13
ID Registers
8.6.13.1
ManufactureID Register (SMBus address = FEh) [reset = 0040h]
Table 45.
ManufactureID Register Field Descriptions
8.6.13.2
Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
Table 46.
Device ID (DeviceAddress) Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
ACP-ACN Input Filter
9.2.2.2
Inductor Selection
9.2.2.3
Input Capacitor
9.2.2.4
Output Capacitor
9.2.2.5
Power MOSFETs Selection
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.2.1
Layout Consideration of Current Path
11.2.2
Layout Consideration of Short Circuit Protection
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
デベロッパー・ネットワークの製品に関する免責事項
12.2
ドキュメントのサポート
12.2.1
関連資料
12.3
ドキュメントの更新通知を受け取る方法
12.4
コミュニティ・リソース
12.5
商標
12.6
静電気放電に関する注意事項
12.7
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
RSN|32
MPQF194B
サーマルパッド・メカニカル・データ
RSN|32
QFND189E
発注情報
jajsd77a_oa
jajsd77a_pm
4
改訂履歴
Changes from * Revision (May 2017) to A Revision
Deleted 「特長」から「補完モードでの理想的なダイオード動作」を
Go
Changed 「特長」の「薄型」を削除、「2.2µH～3.3µH」を
Go
Added 「特長」に「内蔵されたADCにより電圧、電流、電力を監視」を
Go
Changed 「概要」の「入力電源の過負荷」を「システムの故障」に
Go
Changed 18.5 V for 3-cell, and 19.5 for 4-cell to 19.5 V for 3-cell/4-cell in CELL_BATPRESZ description
Go
Changed I to O for CMPOUT I/O
Go
Changed V
(IADP)
to V
(IADPT)
in IADPT description
Go
Deleted minimum 10-ms and added minimum to
PROCHOT
description
Go
Changed REG0x3B to REG0x3D in V
DPM_REG_ACC
Test Conditions in
Electrical Characteristics
Go
Changed REG0x3D to REG0x3B in V
OTG_REG_ACC
Test Conditions in
Electrical Characteristics
Go
Changed REG0x12[15] = 0 to REG0x12[15] = 1 in Test Conditions for I
BAT_BATFET_ON
Go
Changed REG0x12[15] = 0 to REG0x12[15] = 1 in Test Conditions for I
BAT_BATFET_ON
Go
Changed I
BATOVP
test condition from: on SRP and SRN to: on VSYS pin
Go
Added overbar to (BATDRV) in heading
Go
Added overbar to PROCHOT in Overview
Go
Changed 18.5V to 19.5V in 3S row SYSOVP column in
Table 1
Go
Changed 0 to 0 A, lowside to low-side, and LSFET turn-on to LSFET turn-on when the HSFET is off in
Continuous Conduction Mode (CCM)
Go
Changed
Pulse Frequency Modulation (PFM)
Go
Changed during forward mode to during forward supplement mode in
High-Accuracy Current Sense Amplifier (IADPT and IBAT)
Go
Changed
Processor Hot Indication
Go
Changed IADP to IADPT in
Figure 13
Go
Changed bq2570x to bq2570xA in
Figure 14
Go
Added overbar to PROCHOT in
PROCHOT Status
Go
Changed subscript of I
LIM2_VTH
in
Input Overcurrent Protection (ACOC)
Go
Changed 3s – 18.5 V to 3s/4s – 19.5 V in
System Overvoltage Protection (SYSOVP)
Go
Added REG to
Battery Charging
Go
Changed 0 mA – 6350 mA to 50 mA – 6400 mA for 3Fh in
Table 6
Go
Changed Device Address to DeviceID for FFh in
Table 6
Go
Added <default at POR> to PWM_FREQ description in
Table 7
Go
Added sentence to IBAT_GAIN description in
Table 8
Go
Changed LDO to internal resistor in EN_LDO description in
Table 8
Go
Deleted Independent Comparator Reference in
Table 10
Go
Deleted Independent Comparator Polarity in
Table 10
Go
Deleted Independent Comparator Deglitch Time in
Table 10
Go
Added independent to FORCE_LATCHOFF description in
Table 10
Go
Added <default at POR> to BATFETOFF_ HIZ description in
Table 14
Go
Added <default at POR> to PSYS_OTG_ IDCHG description in
Table 14
Go
Added
PROCHOT
Pulse Extension Enable to EN_PROCHOT_EXT description in
Table 16
Go
Added There is a 128 mA offset. to IDCHG_VTH description in
Table 17
Go
Changed 0 mA to 000000b in IDCHG_VTH description in
Table 17
Go
Changed text in
ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
Go
Deleted text and changed larger to 20-mΩ in
Input Current Registers
Go
Added paragraph to
IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
Go
Changed Minimum System Voltage from 614 mV to 6144 mV in
Design Requirements
Go
Deleted Input Snubber and Filter for Voltage Spike Damping section
Go