JAJSNV5 データシート

JAJSNV5G February 1998 – October 2022 CD54HC73 , CD74HC73 , CD74HCT73

PRODUCTION DATA

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

5.6 Switching Specifications

Input, t_r, t_f = 6 ns

PARAMETER		TEST CONDITIONS	V_CC (V)	25℃			–40℃ to 85℃		–55℃ to 125℃		UNIT
PARAMETER		TEST CONDITIONS	V_CC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNIT
HC TYPES
t_PLH, t_PHL	Propagation delay, CP to Q	C_L = 50 pF	2			160		200		240	ns
		C_L = 50 pF	4.5			32		40		48
		C_L = 15 pF	5		13
		C_L = 50 pF	6			28		34		41
t_PLH, t_PHL	Propagation delay, CP to Q	C_L = 50 pF	2			160		200		240	ns
		C_L = 50 pF	4.5			32		40		48
		C_L = 15 pF	5		13
		C_L = 50 pF	6			28		34		41
t_PLH, t_PHL	Propagation delay, R to Q, Q	C_L = 50 pF	2			145		180		220	ns
		C_L = 50 pF	4.5			29		36		44
		C_L = 15 pF	5		12
		C_L = 50 pF	6			25		31		38
t_TLH, t_THL	Output transition time	C_L = 50 pF	2			75		95	18	110	ns
			4.5			15		19		22
			6			13		16		19
C_I	Input capacitance					10		10		10	pF
C_PD	Power dissipation capacitance⁽¹⁾⁽²⁾		5		28						pF
HCT TYPES
t_PLH, t_PHL	Propagation delay, CP to Q	C_L = 50 pF	4.5			38		48		57	ns
t_PLH, t_PHL	Propagation delay, CP to Q	C_L = 50 pF	4.5			36		45		54	ns
t_PLH, t_PHL	Propagation delay, R to Q, Q	C_L = 50 pF	4.5			34		43		51	ns
t_TLH, t_THL	Output transition time	C_L = 50 pF	4.5			15		19		22	ns
C_I	Input capacitance					10		10		10	pF
C_PD	Power dissipation capacitance⁽¹⁾⁽²⁾		5		28						pF

(1) C_PD is used to determine the dynamic power consumption, per flip-flop.

(2) P_D = C_PD V_CC²f_i + ∑ C_L V_CC²f_o where f_i = input frequency, f_o = output frequency, C_L = output load capacitance, V_CC = supply voltage.