JAJS245G August   2007  – January 2024 CDCE949 , CDCEL949

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 PLL Frequency Planning

At a given input frequency (ƒIN), use Equation 1 to calculate the output frequency (ƒOUT) of the CDCEx949.

Equation 1. GUID-53523C49-4B75-41C6-9B1A-02FDB5C45A5A-low.gif

where

  • M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL
  • Pdiv (1 to 127) is the output divider

Use Equation 2 to calculate the target VCO frequency (ƒVCO) of each PLL.

Equation 2. GUID-8402508A-4B2F-4503-AF6C-6F06236C15E3-low.gif

The PLL internally operates as fractional divider and requires the following multiplier/divider settings:

  • N
  • P = 4 – int(log2N/M; if P < 0 then P = 0
  • Q = int(N'/M)
  • R = N′ – M × Q

where

N′ = N × 2P

N ≥ M;

80 MHz ≤ ƒVCO ≤ 230 MHz

16 ≤ Q ≤ 63

0 ≤ P ≤ 4

0 ≤ R ≤ 51

Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
→fOUT = 54 MHz→fOUT = 74.25 MHz
→fVCO = 108 MHz→fVCO = 148.50 MHz
→P = 4 – int(log24) = 4 – 2 = 2→P = 4 – int(log25.5) = 4 – 2 = 2
→N' = 4 × 22 = 16→N' = 11 × 22 = 44
→Q = int(16) = 16→Q = int(22) = 22
→R = 16 – 16 = 0→R = 44 – 44 = 0

The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.