JAJS245G August   2007  – January 2024 CDCE949 , CDCEL949

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.3 Recommended Operating Conditions

MINNOMMAXUNIT
VDDDevice supply voltage1.71.81.9V
VDD(OUT)Output Yx supply voltageCDCE9492.33.6V
CDCEL9491.71.9
VILLow level input voltage LVCMOS0.3 × VDDV
VIHHigh level input voltage LVCMOS0.7 × VDDV
VI(thresh)Input voltage threshold LVCMOS0.5 × VDDV
VISInput voltageS001.9V
S1, S2, SDA, SCL,
VIthresh = 0.5 × VDD		03.6
VICLKInput voltage CLK01.9V
IOH /IOLOutput currentVDDout = 3.3 V±12mA
VDDout = 2.5 V±10mA
VDDout = 1.8 V±8mA
CLOutput load LVCMOS10pF
TAOperating free-air temperature–4085°C
CRYSTAL AND VCXO(1)
fXtalCrystal Input frequency (fundamental mode)82732MHz
ESREffective series resistance100Ω
fPRPulling (0 V ≤ VCtrl ≤ 1.8 V)(2)±120±150ppm
V(Ctrl)Frequency control voltage0VDDV
C0/C1Pullability ratio220
CLOn-chip load capacitance at Xin and Xout020pF
(1) For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(2) Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).