JAJS245G August   2007  – January 2024 CDCE949 , CDCEL949

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.8 Timing Requirements: SDA/SCL

over operating free-air temperature range (unless otherwise noted; see Figure 7-9)
MINNOMMAXUNIT
f(SCL)SCL clock frequencyStandard mode0100kHz
Fast mode0400
tsu(START)START setup time (SCL high before SDA low)Standard mode4.7µs
Fast mode0.6
th(START)START hold time (SCL low after SDA low)Standard mode4µs
Fast mode0.6
tw(SCLL)SCL low-pulse durationStandard mode4.7µs
Fast mode1.3
tw(SCLH)SCL high-pulse durationStandard mode4µs
Fast mode0.6
th(SDA)SDA hold time (SDA valid after SCL low)Standard mode03.45µs
Fast mode00.9
tsu(SDA)SDA setup timeStandard mode250ns
Fast mode100
trSCL/SDA input rise timeStandard mode1000ns
Fast mode300
tfSCL/SDA input fall time300ns
tsu(STOP)STOP setup timeStandard mode4µs
Fast mode0.6
tBUFBus free time between a STOP and START conditionStandard mode4.7µs
Fast mode1.3