SCAS922A February   2012  – April 2016 CDCM9102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Crystal Input (XIN) Interface
      2. 9.4.2 Interfacing between LVPECL and HCSL (PCI Express)
    5. 9.5 Programming
      1. 9.5.1 Device Configuration
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Time Estimation
      2. 10.1.2 Output Termination
      3. 10.1.3 LVPECL Termination
      4. 10.1.4 LVDS Termination
      5. 10.1.5 LVCMOS Termination
      6. 10.1.6 PCI Express Applications
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Calculation Using LCM
        2. 10.2.2.2 Device Configuration
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Management
    2. 11.2 Power Supply Filtering
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RHB Package
32-Pin VQFN
(Top View)

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
POWER SUPPLIES
GND Thermal pad, 14, 22 G Power supply ground and thermal relief
REGCAP1 19 P Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND
REGCAP2 17 P Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND
VDD1 4 P Power Supply, OUT0 clock port
VDD2 1 P Power Supply, OUT1 clock port
VDD3 9 P Power supply, low-noise clock generator
VDD4 16 P Power supply, low-noise clock generator
VDD5 18 P Power supply, low-noise clock generator
VDD6 20 P Power supply, crystal oscillator input
DEVICE CONFIGURATION AND CONTROL
NC 8, 13, 15, 24–32 — No connection permitted
OE 7 O Output enable/shutdown control input (see Table 2)
OS1 10 O Output format select control inputs (see Table 3)
OS0 11 O Output format select control inputs (see Table 3)
RESET 12 I Device reset input (active-low) (see Table 4)(2)
CRYSTAL OSCILLATOR
XIN 21 I Parallel resonant crystal input (25 MHz)
DEVICE OUTPUTS
OSCOUT 23 O Oscillator output port (25 MHz)
OUT0N 5 O Output 0 – negative terminal (100 MHz)
OUT0P 6 O Output 0 – positive terminal (100 MHz)
OUT1N 2 O Output 1 – negative terminal (100 MHz)
OUT1P 3 O Output 1 – positive terminal (100 MHz)
(1) G = Ground, I = Input, O = Output, P = Power
(2) For proper device startup, it is recommended that a capacitor be installed from pin 12 to GND. See Start-Up Time Estimation for more details.