JAJSAQ5F December   2007  – October 2016 DAC121C081 , DAC121C085

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifier
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Serial Interface
        1. 8.3.4.1 Basic I2C Protocol
        2. 8.3.4.2 Standard-Fast Mode
        3. 8.3.4.3 High-Speed (Hs) Mode
        4. 8.3.4.4 I2C Slave (Hardware) Address
      5. 8.3.5 Power-On Reset
      6. 8.3.6 Simultaneous Reset
      7. 8.3.7 Additional Timing Information: toutz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Writing to the DAC Register
      2. 8.5.2 Reading from the DAC Register
    6. 8.6 Registers
      1. 8.6.1 DAC Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation
      2. 9.1.2 DSP/Microprocessor Interfacing
        1. 9.1.2.1 Interfacing to the 2-wire Bus
        2. 9.1.2.2 Interfacing to a Hs-mode Bus
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの関連用語
        1. 12.1.1.1 仕様の定義
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Bipolar Operation

The DAC121C081 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 27. This circuit provides an output voltage range of ±5 V. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5 V.

DAC121C081 DAC121C085 30004917.gif Figure 27. Bipolar Operation

The output voltage of this circuit for any code is found to be, as shown in Equation 2:

Equation 2. VO = (VA × (D / 4096) × ((R1 + R2) / R1) – VA × R2 / R1)

where

Equation 3 shows that with VA = 5 V and R1 = R2,

Equation 3. VO = (10 × D / 4096) – 5 V

A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.

Table 2. Some Rail-to-Rail Amplifiers

AMP PKGS  Typ VOS Typ ISUPPLY
LMP7701 SOT-23 37 uV 0.79 mA
LMV841 SC70-5 50 uV 1 mA
LMC7111 SOT-23 0.9 mV 25 µA
LM7301 SO-8, SOT-23 0.03 mV 620 µA
LM8261 SOT-23 0.7 mV 1 mA

9.1.2 DSP/Microprocessor Interfacing

Interfacing the DAC121C081 to microprocessors and DSPs is quite simple. The following guidelines are offered to simplify the design process.

9.1.2.1 Interfacing to the 2-wire Bus

Figure 28 shows a microcontroller interfacing to the DAC121C081 through the 2-wire bus. Pullup resistors (Rp) should be chosen to create an appropriate bus rise time and to limit the current that will be sunk by the open-drain outputs of the devices on the bus. See the I2C® Specification for further details. Typical pullup values to use in Standard-Fast mode bus applications are 2 kΩ to 10 kΩ. SCL and SDA series resisters (RS) near the DAC121C081 are optional. If high-voltage spikes are expected on the 2-wire bus, series resistors should be used to filter the voltage on SDA and SCL. The value of the series resistance must be picked to ensure the VIL threshold can be achieved. If used, RS is typically 51 Ω.

DAC121C081 DAC121C085 30004909.gif Figure 28. Serial Interface Connection Diagram

9.1.2.2 Interfacing to a Hs-mode Bus

Interfacing to a Hs-mode bus is very similar to interfacing to a Standard-Fast mode bus. In Hs-mode, the specified rise time of SCL is shortened. To create a faster rise time, the master device (microcontroller) can drive the SCL bus high and low. In other words, the microcontroller can drive the line high rather than leaving it to the pullup resistor. It is also possible to decrease the value of the pullup resistors or increase the pullup current to meet the tighter timing specs. See the I2C® Specification for further details.

9.2 Typical Application

DAC121C081 DAC121C085 DAC_applic_I2C_circuit_snas395.gif Figure 29. Pressure Sensor Gain Adjust

9.2.1 Design Requirements

A positive supply only data acquisition system capable of digitizing a pressure sensor output. In addition to digitizing the pressure sensor output, the system designer can use the DAC121C081 to correct for gain errors in the pressure sensor output by adjusting the bias voltage to the bridge pressure sensor.

9.2.2 Detailed Design Procedure

As shown in Equation 4, the output of the pressure sensor is relative to the imbalance of the resistive bridge times the output of the DAC121C081, thus providing the desired gain correction.

Equation 4. Pressure Sensor Output = (DAC_Output × [(R2 / (R1 + R2) – (R4 / (R3 + R4)]

Likewise for the ADC161S626, Equation 5 shows that the ADC output is function of the Pressure Sensor Output times relative to the ratio of the ADC input divided by the DAC121C081 output voltage.

Equation 5. ADC161S626 Output = (Pressure Sensor Output × 100 /(2 × VREF) ) × 216

9.2.3 Application Curve

DAC121C081 DAC121C085 30004920.png Figure 30. INL vs Input Code