JAJSES1D August   2013  – February 2018 DAC3151 , DAC3161 , DAC3171

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     DAC31x1のシステム・ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: DAC3151
    2.     Pin Functions: DAC3161
    3.     Pin Functions: DAC3171 7-Bit Interface Mode
    4.     Pin Functions: DAC3171 14-Bit Interface Mode
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC Specifications
    6. 6.6 Electrical Characteristics: AC Specifications
    7. 6.7 Electrical Characteristics: Digital Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Data Input Formats
      2. 7.3.2 Serial Interface
        1. Table 1. Instruction Byte of the Serial interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Synchronization Modes
      2. 7.4.2 Alarm Monitoring
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1  Register Name: config0 – Address: 0x00, Default: 0x4FC
        1. Table 6. Register Name: config0 – Address: 0x00, Default: 0x4FC
      2. 7.6.2  Register Name: config1 – Address: 0x01, Default: 0x600E
        1. Table 7. Register Name: config1 – Address: 0x01, Default: 0x600E
      3. 7.6.3  Register Name: config2 – Address: 0x02, Default: 0x3FFF
        1. Table 8. Register Name: config2 – Address: 0x02, Default: 0x3FFF
      4. 7.6.4  Register Name: config3 – Address: 0x03, Default: 0x0000
        1. Table 9. Register Name: config3 – Address: 0x03, Default: 0x0000
      5. 7.6.5  Register Name: config4 – Address: 0x04, Default: 0x0000
        1. Table 10. Register Name: config4 – Address: 0x04, Default: 0x0000
      6. 7.6.6  Register Name: config5 – Address: 0x05, Default: 0x0000
        1. Table 11. Register Name: config5 – Address: 0x05, Default: 0x0000
      7. 7.6.7  Register Name: config6 – Address: 0x06, Default: 0x0010(DAC3171); 0x0094(DAC3161); 0x0098(DAC3151)
        1. Table 12. Register Name: config6 – Address: 0x06, Default: 0x0010(DAC3171); 0x0094(DAC3161); 0x0098(DAC3151)
      8. 7.6.8  Register Name: config7 – Address: 0x07, Default: 0xFFFF
        1. Table 13. Register Name: config7 – Address: 0x07, Default: 0xFFFF
      9. 7.6.9  Register Name: config8 – Address: 0x08, Default: 0x6000
        1. Table 14. Register Name: config8 – Address: 0x08, Default: 0x6000
      10. 7.6.10 Register Name: config9 – Address: 0x09, Default: 0x8000
        1. Table 15. Register Name: config9 – Address: 0x09, Default: 0x8000
      11. 7.6.11 Register name: config10 – Address: 0x0A, Default: 0xF080
        1. Table 16. Register Name: config10 – Address: 0x0A, Default: 0xF080
      12. 7.6.12 Register Name: config11 – Address: 0x0B, Default: 0x1111
        1. Table 17. Register Name: config11 – Address: 0x0B, Default: 0x1111
      13. 7.6.13 Register Name: config12 – Address: 0x0C, Default: 0x3A7A
        1. Table 18. Register Name: config12 – Address: 0x0C, Default: 0x3A7A
      14. 7.6.14 Register Name: config13 – Address: 0x0D, Default: 0x36B6
        1. Table 19. Register Name: config13 – Address: 0x0D, Default: 0x36B6
      15. 7.6.15 Register Name: config14 – Address: 0x0E, Default: 0x2AEA
        1. Table 20. Register name: config14 – Address: 0x0E, Default: 0x2AEA
      16. 7.6.16 Register name: config15 – Address: 0x0F, Default: 0x0545
        1. Table 21. Register Name: config15 – Address: 0x0F, Default: 0x0545
      17. 7.6.17 Register Name: config16 – Address: 0x10, Default: 0x0585
        1. Table 22. Register Name: config16 – Address: 0x10, Default: 0x0585
      18. 7.6.18 Register Name: config17 – Address: 0x11, Default: 0x0949
        1. Table 23. Register Name: config17 – Address: 0x11, Default: 0x0949
      19. 7.6.19 Register Name: config18 – Address: 0x12, Default: 0x1515
        1. Table 24. Register Name: config18 – Address: 0x12, Default: 0x1515
      20. 7.6.20 Register Name: config19 – Address: 0x13, Default: 0x3ABA
        1. Table 25. Register Name: config19 – Address: 0x13, Default: 0x3ABA
      21. 7.6.21 Register Name: config20– Address: 0x14, Default: 0x0000
        1. Table 26. Register Name: config20– Address: 0x14, Default: 0x0000
      22. 7.6.22 Register Name: config21– Address: 0x15, Default: 0xFFFF
        1. Table 27. Register Name: config21– Address: 0x15, Default: 0xFFFF
      23. 7.6.23 Register Name: config22– Address: 0x16, Default: 0x0000
        1. Table 28. Register Name: config22– Address: 0x16, Default: 0x0000
      24. 7.6.24 Register Name: config23– Address: 0x17, Default: 0x0000
        1. Table 29. Register Name: config23– Address: 0x17, Default: 0x0000
      25. 7.6.25 Register Name: config24– Address: 0x18, Default: 0x0000
        1. Table 30. Register Name: config24– Address: 0x18, Default: 0x0000
      26. 7.6.26 Register Name: config25– Address: 0x19, Default: 0x0000
        1. Table 31. Register Name: config25– Address: 0x19, Default: 0x0000
      27. 7.6.27 Register Name: config127– Address: 0x7F, Default: 0x0045
        1. Table 32. Register Name: config127– Address: 0x7F, Default: 0x0045
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 仕様の定義
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGC Package
64-Pin VQFN
Top View
DAC3151 DAC3161 DAC3171 PO_51_las959.gif

Pin Functions: DAC3151

PIN I/O DESCRIPTION
NAME NO.
CONTROL OR SERIAL
SCLK 43 I Serial interface clock. Internal pulldown.
SDENB 42 I Serial data enable. Internal pullup.
SDIO 44 I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register sif4_ena (config 0, bit 9)), the SDIO pin in an input only. Internal pulldown.
SDO 46 O Uni-directional serial interface data in 4 pin mode (register sif4_ena (config 0, bit 9)). The SDO pin is tri-stated in 3-pin interface mode (default). Internal pulldown.
RESETB 41 I Serial interface reset input. Active low. Initialized internal registers during high to low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be needed to reinitialize all SPI registers to their default values.
ALARM 47 O CMOS output for ALARM condition.
TXENABLE 48 I Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal pulldown.
SLEEP 49 I Puts device in sleep, active high. Internal pulldown.
DATA INTERFACE
DATA[9:0]P,
DATA[9:0]N		 9, 10, 19,
20, 22, 23,
26, 27, 29,
30, 31, 32		 I LVDS input data bits for both channels. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. The data format relative to DATACLKP and DATACLKN clock is Double Data Rate (DDR) with two data transfers per DATACKP and DATACKN clock cycle.
The data format is interleaved with channel A (rising edge) and channel B (falling edge).
In the default mode (reverse bus not enabled):
DATA13P and DATA13N are most significant data bit (MSB)
DATA0P and DATA0N are least significant data bit (LSB)
DATACLKP,
DATACLKN		 24, 25 I DDR differential input data clock. Edge to center nominal timing. Channel A rising edge, channel B falling edge in multiplexed output mode.
SYNCP,
SYNCN		 6, 7 I Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP and DATACLKN. The signal captured by the falling edge of DATACLKP and DATACLKN.
ALIGNP,
ALIGNN		 4, 5 I LVPECL FIFO output synchronization. This positive and negative pair is captured with the rising edge of DACCLKP and DACCLKN. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can be left unconnected.
OUTPUT OR CLOCK
DACCLKP,
DACCLKN		 1, 2 I LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18 / 2.
IOUTAP,
IOUTAN		 61, 60 O A-channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
REFERENCE
EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output.
BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND.
POWER SUPPLY
IOVDD 45 I Supply voltage for CMOS IO’s. 1.8 V to 3.3 V.
CLKVDD18 3 I 1.8 V clock supply
DIGVDD18 21, 28 I 1.8 V digital supply. Also supplies LVDS receivers.
VDDA18 50, 64 I Analog 1.8 V supply
VDDA33 55, 56, 59 I Analog 3.3 V supply
VFUSE 8 I Digital supply voltage. (1.8 V) This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation.
NC 33, 34, 39,
40, 51, 52,
53, 54,
62, 63		 – Not used. These pins can be left open or tied to GROUND in actual application use. It is recommended to turn off pin 33-40 (register lvdsdata_ena) to save power.
RGC Package
64-Pin VQFN
Top View
DAC3151 DAC3161 DAC3171 PO_61_las959.gif

Pin Functions: DAC3161

PIN I/O DESCRIPTION
NAME NO.
CONTROL OR SERIAL
SCLK 43 I Serial interface clock. Internal pulldown.
SDENB 42 I Serial data enable. Internal pullup.
SDIO 44 I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register sif4_ena (config 0, bit 9)), the SDIO pin in an input only. Internal pulldown.
SDO 46 O Uni-directional serial interface data in 4 pin mode (register sif4_ena (config 0, bit 9)). The SDO pin is tri-stated in 3-pin interface mode (default). Internal pulldown.
RESETB 41 I Serial interface reset input. Active low. Initialized internal registers during high to low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be needed to reinitialize all SPI registers to their default values.
ALARM 47 O CMOS output for ALARM condition.
TXENABLE 48 I Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal pulldown.
SLEEP 49 I Puts device in sleep, active high. Internal pulldown.
DATA INTERFACE
DATA[11:0]P,
DATA[11:0]N		 9, 10, 19,
20, 22, 23,
26, 27, 29,
30, 35, 36		 I LVDS input data bits for both channels. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. The data format relative to DATACLKP and DATACLKN clock is Double Data Rate (DDR) with two data transfers per DATACKP and DATACKN clock cycle.
The data format is interleaved with channel A (rising edge) and channel B (falling edge).
In the default mode (reverse bus not enabled):
DATA13P and DATA13N are most significant data bit (MSB)
DATA0P and DATA0N are least significant data bit (LSB)
DATACLKP,
DATACLKN		 24, 25 I DDR differential input data clock. Edge to center nominal timing. Channel A rising edge, channel B falling edge in multiplexed output mode.
SYNCP,
SYNCN		 6, 7 I Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP and DATACLKN. The signal captured by the falling edge of DATACLKP and DATACLKN.
ALIGNP,
ALIGNN		 4, 5 I LVPECL FIFO output synchronization. This positive or negative pair is captured with the rising edge of DACCLKP and DACCLKN. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can be left unconnected.
OUTPUT OR CLOCK
DACCLKP,
DACCLKN		 1, 2 I LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18 / 2.
IOUTAP,
IOUTAN		 61, 60 O A-channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
REFERENCE
EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output.
BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND.
POWER SUPPLY
IOVDD 45 I Supply voltage for CMOS IO’s. 1.8 V to 3.3 V.
CLKVDD18 3 I 1.8 V clock supply
DIGVDD18 21, 28 I 1.8 V digital supply. Also supplies LVDS receivers.
VDDA18 50, 64 I Analog 1.8 V supply
VDDA33 55, 56, 59 I Analog 3.3 V supply
VFUSE 8 I Digital supply voltage. (1.8 V) This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation.
NC 37, 38, 39,
40, 51, 52,
53, 54,
62, 63		 – Not used. These pins can be left open or tied to GROUND in actual application use. It is recommended to turn off pin 37-40 (register lvdsdata_ena) to save power.
RGC Package
64-Pin VQFN
Top View
DAC3151 DAC3161 DAC3171 PO_71_7bit_int_las959.gif

Pin Functions: DAC3171 7-Bit Interface Mode

PIN I/O DESCRIPTION
NAME NO.
CONTROL OR SERIAL
SCLK 43 I Serial interface clock. Internal pulldown.
SDENB 42 I Serial data enable. Internal pullup.
SDIO 44 I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register XYZ), the SDIO pin in an input only. Internal pulldown.
SDO 46 O Uni-directional serial interface data in 4 pin mode (register XYZ). The SDO pin is tri-stated in 3-pin interface mode (default). Internal pulldown.
RESETB 41 I Serial interface reset input. Active low. Initialized internal registers during high to low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be needed to reinitialize all SPI registers to their default values.
ALARM 47 O CMOS output for ALARM condition.
TXENABLE 48 I Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal pulldown.
SLEEP 49 I Puts device in sleep, active high. Internal pulldown.
DATA INTERFACE
DA[6:0]P,
DA[6:0]N		 9, 10, 19,
20, 22, 23		 I LVDS positive input data bits for channel A. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. The data format relative to DA_CLKP and DA_CLKN clock is Double Data Rate (DDR) with two data transfers per DA_CLKP and DA_CLKN clock cycle.
The data format is 7 MSBs (rising edge) or 7 LSBs (falling edge).
In the default mode (reverse bus not enabled):
D6P and D6N are most significant data bit (MSB)
D0P and D0N are least significant data bit (LSB)
DA_CLKP,
DA_CLKN		 6, 7 I DDR differential input data clock for channel A. Edge to center nominal timing. Assumes SPI register field dual_ena (bit0 of Config3) is set. Otherwise, DA_CLKP and DA_CLKN will be on pins 24 or 25 as in DAC3171 14-bit Interface Mode.
OUTPUT OR CLOCK
DACCLKP,
DACCLKN		 1, 2 I LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18 / 2.
IOUTAP,
IOUTAN		 61, 60 O A-channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current source and the most positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current source and the least positive voltage on the IOUTA1 pin. The IOUTA2 pin is the complement of IOUTA1.
REFERENCE
EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output.
BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND.
POWER SUPPLY
IOVDD 45 I Supply voltage for CMOS IO’s. 1.8 V to 3.3 V.
CLKVDD18 3 I 1.8 V clock supply
DIGVDD18 21, 28 I 1.8 V digital supply. Also supplies LVDS receivers.
VDDA18 50, 64 I Analog 1.8 V supply
VDDA33 55, 56, 59 I Analog 3.3 V supply
VFUSE 8 I Digital supply voltage. (1.8 V) This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation.
NC 4, 5, 24,
25, 26, 27,
29, 30-39,
40, 51, 52,
53, 62, 63		 – Not used. Pin 4 can be left open or tied to DIGVDD18, and other pins can be left open or tied to GROUND in actual application use. It is recommended to turn off pin 24, 25, 26, 27, 29, 30-39, and 40 (register lvdsdataclk_ena, lvdsdata_ena) to save power.
RGC Package
64-Pin VQFN
Top View
DAC3151 DAC3161 DAC3171 PO_71_14bit_int_las959.gif

Pin Functions: DAC3171 14-Bit Interface Mode

PIN I/O DESCRIPTION
NAME NO.
CONTROL OR SERIAL
SCLK 43 I Serial interface clock. Internal pulldown.
SDENB 42 I Serial data enable. Internal pullup.
SDIO 44 I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register sif4_ena (config 0, bit 9)), the SDIO pin in an input only. Internal pulldown.
SDO 46 O Uni-directional serial interface data in 4 pin mode (register sif4_ena (config 0, bit 9)). The SDO pin is tri-stated in 3-pin interface mode (default). Internal pulldown.
RESETB 41 I Serial interface reset input. Active low. Initialized internal registers during high to low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be needed to reinitialize all SPI registers to their default values.
ALARM 47 O CMOS output for ALARM condition.
TXENABLE 48 I Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal pulldown.
SLEEP 49 I Puts device in sleep, active high. Internal pulldown.
DATA INTERFACE
DATA[13:0]P,
DATA[13:0]N		 9, 10-19,
20, 22, 23,
26, 27, 29,
30-39, 40		 I LVDS input data bits for both channels. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. The data format relative to DATACLKP and DATACLKN clock is Double Data Rate (DDR) with two data transfers per DATACKP and DATACKN clock cycle.
The data format is interleaved with channel A (rising edge) and channel B (falling edge).
In the default mode (reverse bus not enabled):
DATA13P and DATA13N are most significant data bit (MSB)
DATA0P and DATA0N are least significant data bit (LSB)
DATACLKP,
DATACLKN		 24, 25 I DDR differential input data clock. Edge to center nominal timing. Channel A rising edge, channel B falling edge in multiplexed output mode.
SYNCP,
SYNCN		 6, 7 I Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP and DATACLKN. The signal captured by the falling edge of DATACLKP and DATACLKN.
ALIGNP,
ALIGNN		 4, 5 I LVPECL FIFO output synchronization. This positive or negative pair is captured with the rising edge of DACCLKP and DACCLKN. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can be left unconnected.
OUTPUT OR CLOCK
DACCLKP,
DACCLKN		 1, 2 I LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18 / 2.
IOUTAP,
IOUTAN		 61, 60 O A-channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
REFERENCE
EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output.
BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND.
POWER SUPPLY
IOVDD 45 I Supply voltage for CMOS IO’s, 1.8 V to 3.3 V.
CLKVDD18 3 I 1.8 V clock supply
DIGVDD18 21, 28 I 1.8 V digital supply. Also supplies LVDS receivers.
VDDA18 50, 64 I Analog 1.8 V supply
VDDA33 55, 56, 59 I Analog 3.3 V supply
VFUSE 8 I Digital supply voltage. (1.8 V) This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation.
NC 51–54,
62, 63		 – Not used. These pins can be left open or tied to GROUND in actual application use.