JAJSSA9
November 2023
DAC61401
,
DAC81401
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
5.7
Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
5.8
Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
5.9
Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
5.10
Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
5.11
Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
5.12
Timing Diagrams
5.13
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Digital-to-Analog Converter (DAC) Architecture
6.3.2
R-2R Ladder DAC
6.3.3
Programmable Gain Output Buffer
6.3.4
Sense Pins
6.3.5
DAC Register Structure
6.3.5.1
Output Update
6.3.5.2
Software Clear
6.3.5.2.1
Software Reset Mode
6.3.6
Internal Reference
6.3.7
Power-Supply Sequence
6.3.7.1
Power-On Reset (POR)
6.3.8
Thermal Alarm
6.4
Device Functional Modes
6.4.1
Power Down Mode
6.5
Programming
6.5.1
Stand-Alone Operation
6.5.2
Daisy-Chain Operation
6.5.3
Frame Error Checking
7
Register Map
7.1
Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Key Components
8.2.2.2
Compensation Capacitor
8.2.2.3
Gain Stage
8.2.2.4
Attenuation and Buffer Stage
8.2.2.5
External Power Supply
8.2.2.6
Protection Design
8.2.2.7
Design Accuracy
8.2.3
Application Curves
8.3
Initialization Set Up
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
ドキュメントの更新通知を受け取る方法
9.2
サポート・リソース
9.3
Trademarks
9.4
静電気放電に関する注意事項
9.5
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PW|20
MPDS362A
サーマルパッド・メカニカル・データ
発注情報
jajssa9_oa
8.2.2.1
Key Components
U1, U2—OPA593 85‑V, low-offset, low-noise, 10‑MHz, 250‑mA output current, precision operational amplifier
U3—OPA189 36-V, low-offset, low-drift, low-noise, 14‑MHz precision operational amplifier
D1, D2, D4, D5, D7, D8—Schottky diode 100‑V, 150‑mA, 0.7‑V forward voltage, fast switching
D3, D6—85‑V standoff voltage, high‑current, bidirectional TVS
R1, R2—low temperature coefficient and high accuracy (< 0.01%) thin film resistors
R5, R6—low temperature coefficient and high accuracy (< 0.01%) thin film resistors