JAJSSA9 November 2023 DAC61401 , DAC81401
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE(1) | ||||||
Resolution | DAC81401 | 16 | Bits | |||
DAC61401 | 12 | Bits | ||||
INL | Relative accuracy(1) | DAC81401, all ranges except 0-V to 40-V range |
–1 | ±0.4 | 1 | LSB |
DAC81401, 0-V to 40-V range | –2 | 2 | LSB | |||
DAC61401 | –1 | 1 | LSB | |||
DNL | Differential nonlinearity | –1 | ±0.3 | 1 | LSB | |
TUE | Total unadjusted error(1) | Unipolar ranges, AVSS = 0 V | –0.09 | 0.09 | %FSR | |
Unipolar ranges, AVSS = 0 V, 0°C ≤ TA ≤ +50°C |
–0.07 | 0.07 | ||||
Bipolar ranges, –21.5 V ≤ AVSS < 0 V | –0.085 | 0.085 | ||||
OE | Offset error(1) | Unipolar ranges, AVSS = 0 V Bipolar ranges, –21.5 V ≤ AVSS < 0 V |
–0.05 | 0.05 | %FSR | |
OE-TC | Offset error temperature coefficient | Unipolar ranges, AVSS = 0 V Bipolar ranges, –21.5 V ≤ AVSS < 0 V |
±2 | ppmFSR/°C | ||
ZCE | Zero-code (negative full scale) error | Unipolar ranges, AVSS = 0 V | 0.1 | %FSR | ||
Bipolar ranges, –21.5 V ≤ AVSS < 0 V | 0.05 | |||||
ZCE-TC | Zero-code (negative full scale) error temperature coefficient | Unipolar ranges, AVSS = 0 V Bipolar ranges, –21.5 V ≤ AVSS < 0 V |
±2 | ppmFSR/°C | ||
FSE | Full-scale error(2) | Unipolar ranges, AVSS = 0 V Bipolar ranges, –21.5 V ≤ AVSS < 0 V |
–0.08 | 0.08 | %FSR | |
FSE-TC | Full-scale error temperature coefficient(2) | ±3 | ppmFSR/°C | |||
GE | Gain error(1) | Unipolar ranges, AVSS = 0 V | –0.075 | 0.075 | %FSR | |
BPGE | Gain error(1) | Bipolar ranges, –21.5 V ≤ AVSS < 0 V | –0.065 | 0.065 | %FSR | |
GE-TC | Gain error temperature coefficient | ±2 | ppmFSR/°C | |||
BPZE | Bipolar zero (midscale) error | Bipolar ranges, –21.5 V ≤ AVSS < 0 V | –0.03 | 0.03 | %FSR | |
BPZE-TC | Bipolar zero (midscale) error temperature coefficient | Bipolar ranges, –21.5 V ≤ AVSS < 0 V | ±2 | ppmFSR/°C | ||
Output voltage drift over time | TA = 40°C, DAC code at full-scale, 1000 hours | ±6 | ppm FSR | |||
OUTPUT CHARACTERISTICS | ||||||
VOUT | Output voltage | 0 | 5 | V | ||
20% overrange of 0 V to 5 V | 0 | 6 | ||||
0 | 10 | |||||
20% overrange of 0 V to 10 V | 0 | 12 | ||||
0 | 20 | |||||
20% overrange of 0 V to 20 V | 0 | 24 | ||||
0 | 40 | |||||
–5 | 5 | |||||
20% overrange of –5 V to +5 V | –6 | 6 | ||||
–10 | 10 | |||||
20% overrange of –10 V to +10 V | –12 | 12 | ||||
–20 | 20 | |||||
Output voltage headroom (to AVDD) and footroom (to AVSS)(4) | –10 mA ≤ load current ≤ 10 mA | 1.25 | ||||
5.5 V < AVDD ≤ 41.5 V, −15 mA ≤ load current ≤ +15 mA |
1.5 | V | ||||
IOS | Short-circuit current(3) | Full-scale output shorted to AVSS | 40 | mA | ||
Full-scale output shorted to AVDD, 5.5 V < AVDD ≤ 41.5 V, |
40 | |||||
Zero-scale output shorted to AVDD, 4.5 V ≤ AVDD ≤ 5.5 V |
25 | |||||
Load regulation | DAC at midscale, –15 mA ≤ load current ≤ +15 mA |
50 | µV/mA | |||
CL | Capacitive load(4) | RLOAD = open, CCOMP pin left floating |
0 | 2 | nF | |
RLOAD = open, CCOMP pin = 470 pF ±10% to VOUT |
1 | µF | ||||
IL | Load current(4) | 5.5 V < AVDD ≤ 41.5 V | 15 | mA | ||
4.5 V < AVDD ≤ 5.5 V | 10 | |||||
VOUT dc output impedance | DAC code at midscale, DAC unloaded | 0.05 | Ω | |||
DAC code at full scale, DAC unloaded | 0.05 | |||||
DAC code at zero scale, DAC unloaded, unipolar output |
35 | |||||
DAC code at negative full scale, DAC unloaded, bipolar output |
0.05 | |||||
VSENSEP dc output impedance | DAC code at midscale, 10-V span | 55 | kΩ | |||
DAC disabled | 45 | |||||
DYNAMIC PERFORMANCE | ||||||
Output voltage settling time | 5-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB | 7 | µs | |||
10-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB | 8 | µs | ||||
20-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB | 12 | µs | ||||
40-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB | 22 | µs | ||||
5-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB, CL = 1 µF, CCOMP = 470 pF to VOUT |
0.6 | ms | ||||
10-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB, CL = 1 µF, CCOMP = 470 pF to VOUT |
0.6 | ms | ||||
20-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB, CL = 1 µF, CCOMP = 470 pF to VOUT |
0.6 | ms | ||||
40-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB, CL = 1 µF, CCOMP = 470 pF to VOUT |
1.2 | ms | ||||
SR | Slew rate | 0-V to 5-V range (10% to 90% of full-scale range) | 0.8 | V/µs | ||
All other output ranges except 40-V span (10% to 90% of full-scale range) | 4 | |||||
0-V to 5-V range, CL = 1 µF, CCOMP = 470 pF to VOUT |
0.04 | |||||
All other ranges, CL = 1 µF, CCOMP = 470 pF to VOUT |
0.04 | |||||
Power-on glitch magnitude | AVSS and AVDD ramped symmetrically, ramp rate = 18 V/ms, output unloaded, internal reference | 0.1 | V | |||
Output enable glitch magnitude | AVSS and AVDD ramped, output unloaded, internal reference | 0.35 | V | |||
VNOISEPP | Output noise | 0.1 Hz to 10 Hz, DAC code at midscale, 10-V span, external reference = 2.5 V |
25 | µVpp | ||
0.1 Hz to 10 Hz, DAC code at midscale, 10-V span, internal reference = 2.5 V |
30 | |||||
VNOISE | Output noise density | 1 kHz, DAC code at midscale, 5-V span, output unloaded, external reference |
115 | nV/Hz | ||
10 kHz, DAC code at midscale, 5-V span, output unloaded, external reference |
105 | |||||
THD | Total harmonic distortion | 1-kHz sine wave on VOUT, output unloaded, DAC update rate = 400 kHz | 93 | dB | ||
PSRR-AC | Power supply rejection ratio - ac | VOUT = 0 V (midscale), output unloaded, ±10-V output, frequency = 60 Hz, amplitude 200 mVPP, superimposed on AVDD, VDD or AVSS |
75 | dB | ||
PSRR-DC | Power supply rejection ratio - dc | VOUT = 0 V (midscale), ±10-V output, VDD = 5 V, AVDD = 15 V ± 20%, AVSS = –15 V, output unloaded |
5 | µV/V | ||
VOUT = 0 V (midscale), ±10-V output, VDD = 5 V, AVDD = 15 V, AVSS = –15 V ± 20%, output unloaded |
10 | µV/V | ||||
VOUT = 0 V (midscale), ±10-V output, VDD = 5 V ± 5%, AVDD = 15 V, AVSS = –15 V, output unloaded |
0.2 | mV/V | ||||
VGL | Code change glitch impulse | 1-LSB change around midscale, 0-V to 5-V range, output unloaded |
1 | nV-s | ||
1-LSB change around midscale, 0-V to 10-V range, output unloaded |
2 | |||||
1-LSB change around midscale, –5-V to +5-V range, output unloaded |
2 | |||||
1-LSB change around midscale, –10-V to +10-V range, output unloaded |
4 | |||||
Code change glitch amplitude | 1-LSB change around midscale, 0-V to 5-V, 0-V to 10-V, –5-V to +5-V, and –10-V to +10-V ranges, output unloaded |
±1.5 | mV | |||
Digital feedthrough | DAC code at midscale, fSCLK = 1 MHz, output unloaded | 0.3 | nV-s | |||
EXTERNAL REFERENCE INPUT | ||||||
VREFIO | Reference input voltage | 2.49 | 2.5 | 2.51 | V | |
IREF | Reference input current | 50 | µA | |||
ZIN | Reference input impedance | 50 | kΩ | |||
CREF | Reference input capacitance | 90 | pF | |||
INTERNAL REFERENCE | ||||||
VREFO | Reference output voltage | TA = 25°C | 2.4975 | 2.5025 | V | |
Reference output drift(3) | 5 | 10 | ppm/°C | |||
RZO | Reference output impedance | 0.15 | Ω | |||
VNOISEPP | Reference output noise | 0.1 Hz to 10 Hz | 12 | µVpp | ||
VNOISE | Reference output noise density | 10 kHz, VREFIO pin = 10 nF | 240 | nV/Hz | ||
IL | Reference load current | Source | 5 | mA | ||
Reference load regulation | Source | 120 | µV/mA | |||
Reference line regulation | 100 | µV/V | ||||
Reference output drift over time | TA = 40°C, 1000 hours | ±300 | µV | |||
Reference thermal hysteresis | First cycle | ±400 | µV | |||
Additional cycle | ±35 | |||||
DIGITAL INPUTS AND OUTPUTS | ||||||
VIH | SDIN, high-level input voltage | 0.7 × IOVDD | V | |||
VIL | SDIN, low-level input voltage | 0.3 × IOVDD | V | |||
Input current | ±2 | µA | ||||
Input pin capacitance | 2 | pF | ||||
VOH | SDO, high-level output voltage | SDO load current = 0.2 mA | IOVDD – 0.2 | V | ||
VOL | SDO, low-level output voltage | SDO load current = 0.2 mA | 0.4 | V | ||
FAULT, low-level output voltage | FAULT load current = 10 mA | 0.4 | V | |||
Output pin capacitance | 5 | pF | ||||
POWER REQUIREMENTS(5) | ||||||
IAVDD | AVDD supply current(5) | Normal mode, internal reference or external reference | 1.6 | mA | ||
Power down mode | 10 | µA | ||||
IVDD | VDD supply current(5) | Digital interface static, internal reference or external reference | 2.5 | mA | ||
IAVSS | AVSS supply current(5) | Normal mode, internal reference or external reference | –1.6 | mA | ||
Power-down mode | –10 | µA | ||||
IIOVDD | IOVDD supply current(5) | SCLK toggling at 1 MHz | 10 | 120 | µA |