JAJSSA9A November   2023  – December 2024 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - Write, IOVDD = 1.7V to 2.7V
    7. 5.7  Timing Requirements - Write, IOVDD = 2.7V to 5.5V
    8. 5.8  Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 1.7V to 2.7V
    9. 5.9  Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 1.7V to 2.7V
    10. 5.10 Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 2.7V to 5.5V
    11. 5.11 Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 2.7V to 5.5V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

8.2.2.3 Gain Stage

The gain stage amplifies the DAC output voltage by 4 ×. This gain stage uses the OPA593 (U1), which supports an output voltage from 0V to 85V or ±42.5V. At the gain stage output, obtain 0V to 80V ±40V by programming the DAC output 0V to 20V or ±10V, respectively. For a given gain-stage output, calculate the DAC output by the Equation 3:

Equation 3. V O U T = V O U T _ H V 4

Where:

  • VOUT: output voltage of DACx1401
  • VOUT_HV: output of the gain stage (U1) in block diagram

The gain stage output vs DAC output plot is provided in Figure 8-2 and Figure 8-3 for both unipolar and bipolar modes, respectively.