JAJSLD4B august   2020  – july 2023 DLP471TP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2 DMD Power Supply Power-Down Procedure

  • During power-down, VDD and VDDA must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. See Table 9-2.
  • During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
  • During power-down, LVCMOS input pins must be less than specified in Section 6.4.
GUID-85B77355-73DC-479E-92C5-6C0DF9347D27-low.gif
A. See Section 5 for the Pin Functions Table.
B. To prevent excess current, the supply voltage difference |VOFFSET – VBIAS| must be less than the specified limit in Section 6.4.
C. To prevent excess current, the supply difference |VBIAS – VRESET| must be less than the specified limit in Section 6.4.
D. VBIAS should power up after VOFFSET has powered up, per the Delay1 specification in Table 9-2.
E. DLP controller software initiates the global VBIAS command.
F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates DMD_EN_ARSTZ and disables VBIAS, VRESET, and VOFFSET.
G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware DMD_EN_ARSTZ will go low.
H. VDD must remain high until after VOFFSET, VBIAS, VRESET go low, per Delay2 specification in Table 9-2.
I. To prevent excess current, the supply voltage delta |VDDA – VDD| must be less than specified limit in Section 6.4.
Figure 9-1 DMD Power Supply Requirements
Table 9-2 DMD Power-Supply Requirements
PARAMETERDESCRIPTIONMINNOMMAXUNIT
Delay1(1)Delay from VOFFSET settled at recommended operating voltage to VBIAS and VRESET power up12ms
Delay2(1)Delay VDD must be held high from VOFFSET, VBIAS and VRESET powering down.50us
(1) See Figure 9-1.