JAJSLM7A September   2020  – April 2021 DLP5533A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     Illumination Overfill Diagram
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     Electrical and Timing Diagrams
    10. 6.8  Switching Characteristics
    11.     LPSDR and Test Load Circuit Diagrams
    12. 6.9  System Mounting Interface Loads
    13.     System Interface Loads Diagram
    14. 6.10 Physical Characteristics of the Micromirror Array
    15.     Array Physical Characteristics Diagram
    16. 6.11 Micromirror Array Optical Characteristics
    17. 6.12 Window Characteristics
    18. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Temperature Rise Through the Package for Heatsink Design
      2. 7.6.2 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 DMD Handling
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
IDD Supply current: VDD(2) VDD = 1.95 V 310 mA
IDDI Supply current: VDDI(2) VDDI = 1.95 V 55 mA
IOFFSET Supply current: VOFFSET VOFFSET = 8.75 V 6 mA
IBIAS Supply current: VBIAS VBIAS = 16.5 V 1 mA
IRESET Supply current: VRESET VRESET = -10.5 V -4.5 mA
POWER
PDD Supply power dissipation: VDD(2) VDD = 1.95 V 604.5 mW
PDDI Supply power dissipation: VDDI(2) VDDI = 1.95 V 107.25 mW
POFFSET Supply power dissipation: VOFFSET VOFFSET = 8.75 V 52.5 mW
PBIAS Supply power dissipation: VBIAS VBIAS = 16.5 V 16.5 mW
PRESET Supply power dissipation: VRESET VRESET = -10.5 V 47.25 mW
PTOTAL Supply power dissipation: Total 828 mW
LPSDR INPUT (3)
VIH(DC) DC input high voltage 0.7 × VDD VDD + 0.3 V
VIL(DC) DC input low voltage –0.3 0.3 × VDD V
VIH(AC) AC input high voltage 0.8 × VDD VDD + 0.3 V
VIL(AC) AC input low voltage –0.3 0.2 × VDD V
∆VT Hysteresis (VT+ – VT–) See Figure 6-9 0.1 × VDD 0.4 × VDD V
IIL Low–level input current VDD = 1.95 V; VI = 0 V –100 nA
IIH High–level input current VDD = 1.95 V; VI = 1.95 V 300 nA
LPSDR OUTPUT (4)
VOH DC output high voltage IOH = -2mA 0.8 × VDD V
VOL DC output low voltage IOL = 2mA 0.2 × VDD V
CAPACITANCE
CIN Input capacitance LPSDR ƒ = 1 MHz 10 pF
Input capacitance SubLVDS ƒ = 1 MHz 20
COUT Output capacitance ƒ = 1 MHz 10 pF
CRESET Reset group capacitance ƒ = 1 MHz (1152 X 144 micromirrors) 350 400 450 pF
CTEMP Temperature sense diode capacitance ƒ = 1 MHz 20 pF
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) Supply power dissipation based on non–compressed commands and data.
(3) LPSDR input specifications are for pin DMD_DEN_ARSTZ.
(4) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.