DLPS206 May 2021 DLPC7540
PRODUCTION DATA
The DLPC7540 Controller DMD interface supports two High Speed Serial Interface (HSSI) output-only interfaces for data transmission, a single low speed LVDS output-only interface for command write transactions, as well as a low speed single-ended input interface used for command read transactions. Each HSSI port supports full data-only inter-lane remapping within the port, but not between ports. When utilizing this feature, each unique data lane pair can only be mapped to one unique destination data lane pair, and Intra-lane remapping (i.e. swapping P with N) is not supported. In addition, the two HSSI ports can also be swapped. Lane and port remapping (specified in flash) can help with board layout as needed. The number of HSSI ports and number of HSSI lanes/per HSSI port required are based on DMD type and DMD display resolution. Table 7-18 shows some remapping examples. When both ports are used, they do not need to have the same pin mapping.
DLPC7540 Controller PINS - REMAPPING EXAMPLES TO DMD PINS | DMD PINS | |||
---|---|---|---|---|
BASELINE | FLIP HSSI0 180 No FLIP HSSI1 | SWAP HSSI0 PORT WITH HSSI1 PORT | SWAP HSSI0 PORT WITH HSSI1 PORT AND MIXED REMAPPING | |
DMD_HSSI0_D0_P DMD_HSSI0_D0_N | DMD_HSSI0_D7_P DMD_HSSI0_D7_N | DMD_HSSI1_D0_P DMD_HSSI1_D0_N | DMD_HSSI1_D2_P DMD_HSSI1_D2_N | DMD_HSSI0_D0_P DMD_HSSI0_D0_N |
DMD_HSSI0_D1_P DMD_HSSI0_D1_N | DMD_HSSI0_D6_P DMD_HSSI0_D6_N | DMD_HSSI1_D1_P DMD_HSSI1_D1_N | DMD_HSSI1_D3_P DMD_HSSI1_D3_N | DMD_HSSI0_D1_P DMD_HSSI0_D1_N |
DMD_HSSI0_D2_P DMD_HSSI0_D2_N | DMD_HSSI0_D5_P DMD_HSSI0_D5_N | DMD_HSSI1_D2_P DMD_HSSI1_D2_N | DMD_HSSI1_D0_P DMD_HSSI1_D0_N | DMD_HSSI0_D2_P DMD_HSSI0_D2_N |
DMD_HSSI0_D3_P DMD_HSSI0_D3_N | DMD_HSSI0_D4_P DMD_HSSI0_D4_N | DMD_HSSI1_D3_P DMD_HSSI1_D3_N | DMD_HSSI1_D1_P DMD_HSSI1_D1_N | DMD_HSSI0_D3_P DMD_HSSI0_D3_N |
DMD_HSSI0_D4_P DMD_HSSI0_D4_N | DMD_HSSI0_D3_P DMD_HSSI0_D3_N | DMD_HSSI1_D4_P DMD_HSSI1_D4_N | DMD_HSSI1_D6_P DMD_HSSI1_D6_N | DMD_HSSI0_D4_P DMD_HSSI0_D4_N |
DMD_HSSI0_D5_P DMD_HSSI0_D5_N | DMD_HSSI0_D2_P DMD_HSSI0_D2_N | DMD_HSSI1_D5_P DMD_HSSI1_D5_N | DMD_HSSI1_D7_P DMD_HSSI1_D7_N | DMD_HSSI0_D5_P DMD_HSSI0_D5_N |
DMD_HSSI0_D6_P DMD_HSSI0_D6_N | DMD_HSSI0_D1_P DMD_HSSI0_D1_N | DMD_HSSI1_D6_P DMD_HSSI1_D6_N | DMD_HSSI1_D4_P DMD_HSSI1_D4_N | DMD_HSSI0_D6_P DMD_HSSI0_D6_N |
DMD_HSSI0_D7_P DMD_HSSI0_D7_N | DMD_HSSI0_D0_P DMD_HSSI0_D0_N | DMD_HSSI1_D7_P DMD_HSSI1_D7_N | DMD_HSSI1_D5_P DMD_HSSI1_D5_N | DMD_HSSI0_D7_P DMD_HSSI0_D7_N |
DMD_HSSI1_D0_P DMD_HSSI1_D0_N | DMD_HSSI1_D0_P DMD_HSSI1_D0_N | DMD_HSSI0_D0_P DMD_HSSI0_D0_N | DMD_HSSI0_D6_P DMD_HSSI0_D6_N | DMD_HSSI1_D0_P DMD_HSSI1_D0_N |
DMD_HSSI1_D1_P DMD_HSSI1_D1_N | DMD_HSSI1_D1_P DMD_HSSI1_D1_N | DMD_HSSI0_D1_P DMD_HSSI0_D1_N | DMD_HSSI0_D7_P DMD_HSSI0_D7_N | DMD_HSSI1_D1_P DMD_HSSI1_D1_N |
DMD_HSSI1_D2_P DMD_HSSI1_D2_N | DMD_HSSI1_D2_P DMD_HSSI1_D2_N | DMD_HSSI0_D2_P DMD_HSSI0_D2_N | DMD_HSSI0_D4_P DMD_HSSI0_D4_N | DMD_HSSI1_D2_P DMD_HSSI1_D2_N |
DMD_HSSI1_D3_P DMD_HSSI1_D3_N | DMD_HSSI1_D3_P DMD_HSSI1_D3_N | DMD_HSSI0_D3_P DMD_HSSI0_D3_N | DMD_HSSI0_D5_P DMD_HSSI0_D5_N | DMD_HSSI1_D3_P DMD_HSSI1_D3_N |
DMD_HSSI1_D4_P DMD_HSSI1_D4_N | DMD_HSSI1_D4_P DMD_HSSI1_D4_N | DMD_HSSI0_D4_P DMD_HSSI0_D4_N | DMD_HSSI0_D2_P DMD_HSSI0_D2_N | DMD_HSSI1_D4_P DMD_HSSI1_D4_N |
DMD_HSSI1_D5_P DMD_HSSI1_D5_N | DMD_HSSI1_D5_P DMD_HSSI1_D5_N | DMD_HSSI0_D5_P DMD_HSSI0_D5_N | DMD_HSSI0_D3_P DMD_HSSI0_D3_N | DMD_HSSI1_D5_P DMD_HSSI1_D5_N |
DMD_HSSI1_D6_P DMD_HSSI1_D6_N | DMD_HSSI1_D6_P DMD_HSSI1_D6_N | DMD_HSSI0_D6_P DMD_HSSI0_D6_N | DMD_HSSI0_D0_P DMD_HSSI0_D0_N | DMD_HSSI1_D6_P DMD_HSSI1_D6_N |
DMD_HSSI1_D7_P DMD_HSSI1_D7_N | DMD_HSSI1_D7_P DMD_HSSI1_D7_N | DMD_HSSI0_D7_P DMD_HSSI0_D7_N | DMD_HSSI0_D1_P DMD_HSSI0_D1_N | DMD_HSSI1_D7_P DMD_HSSI1_D7_N |