JAJSCY7A December   2014  – December 2015 DRV5053-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Magnetic Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Field Direction Definition
      2. 7.3.2 Device Output
      3. 7.3.3 Power-On Time
      4. 7.3.4 Output Stage
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Overcurrent Protection (OCP)
        2. 7.3.5.2 Load Dump Protection
        3. 7.3.5.3 Reverse Supply Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With No Filter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Filtered Typical Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Typical Noise Versus Cutoff Frequency
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 デバイスの項目表記
      2. 10.1.2 デバイスのマーキング
    2. 10.2 コミュニティ・リソース
    3. 10.3 商標
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The DRV5053-Q1 device is a chopper-stabilized Hall sensor with an analog output for magnetic sensing applications. The DRV5053-Q1 device can be powered with a supply voltage between 2.7 and 38 V, and will survive –22 V reverse battery conditions continuously. Note that the DRV5053-Q1 device will not be operating when approximately –22 to 2.4 V is applied to VCC (with respect to GND). In addition, the device can withstand supply voltages up to 40 V for transient durations.

The output voltage is dependent on the magnetic field perpendicular to the package. The absence of a magnetic field will result in OUT = 1 V. A magnetic field will cause the output voltage to change linearly with the magnetic field.

The field polarity is defined as follows: a south pole near the marked side of the package is a positive magnetic field. A north pole near the marked side of the package is a negative magnetic field.

For devices with a negative sensitivity (that is, DRV5053RA: –40 mV/mT), a south pole will cause the output voltage to drop below 1 V, and a north pole will cause the output to rise above 1 V.

For devices with a positive sensitivity (that is, DRV5053EA: +40 mV/mT), a south pole will cause the output voltage to rise above 1 V, and a north pole will cause the output to drop below 1 V.

7.2 Functional Block Diagram

DRV5053-Q1 5053.gif

7.3 Feature Description

7.3.1 Field Direction Definition

A positive magnetic field is defined as a south pole near the marked side of the package as shown in Figure 7.

DRV5053-Q1 field_direction_slis150.gif
N = North pole, S = South pole
Figure 7. Field Direction Definition

7.3.2 Device Output

The DRV5053-Q1 device output is defined below for negative sensitivity (that is, –45 mV/mT, RA) and positive sensitivity (that is, +45 mV/mT, EA):

DRV5053-Q1 neg_sensitivity_lis151.gif Figure 8. DRV5053-Q1 – Negative Sensitivity
DRV5053-Q1 pos_sensitivity_lis151.gif Figure 9. DRV5053-Q1 – Positive Sensitivity

7.3.3 Power-On Time

After applying VCC to the DRV5053-Q1 device, ton must elapse before OUT is valid. Figure 10 shows Case 1 and Figure 11 shows case 2; the output is defined assuming a negative sensitivity device and a constant magnetic field –BSAT < B < BSAT.

DRV5053-Q1 power_on_1_lis153.gif Figure 10. Case 1: Power On When B < 0, North
DRV5053-Q1 power_on_2_lis153.gif Figure 11. Case 2: Power On When B > 0, South

7.3.4 Output Stage

The DRV5053-Q1 output stage is capable of up to 300-μA of current source or 2.3-mA sink. For proper operation, ensure that equivalent output load ROUT > 10 kΩ.

The capacitive load directly present on the OUT pin should be less than 10 nF to ensure the internal operational amplifier is stable. If an external RC filter is added to reduce noise, it is acceptable to use a resistor ≥ 200 Ω with a capacitor ≤0.1 µF. For an application example, see Filtered Typical Application.

7.3.5 Protection Circuits

An analog current limit circuit limits the current through the output driver. The driver current will be clamped to IOCP

7.3.5.1 Overcurrent Protection (OCP)

An analog current-limit circuit limits the current through the FET. The driver current is clamped to IOCP. During this clamping, the rDS(on) of the output FET is increased from the nominal value.

7.3.5.2 Load Dump Protection

The DRV5053-Q1 device operates at DC VCC conditions up to 38 V nominally, and can additionally withstand VCC = 40 V. No current-limiting series resistor is required for this protection.

7.3.5.3 Reverse Supply Protection

The DRV5053-Q1 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V).

NOTE

In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings specified in the Absolute Maximum Ratings.

Table 1.

FAULT CONDITION DEVICE DESCRIPTION RECOVERY
FET overload (OCP) ISINK ≥ IOCP Operating Output current is clamped to IOCP IO < IOCP
Load Dump 38 V < VCC < 40 V Operating Device will operate for a transient duration VCC ≤ 38 V
Reverse Supply –22 V < VCC < 0 V Disabled Device will survive this condition VCC ≥ 2.7 V

7.4 Device Functional Modes

The DRV5053-Q1 device is active only when VCC is between 2.7 and 38 V.

When a reverse supply condition exists, the device is inactive.