JAJSGV8B September   2019  – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions—DRV8912-Q1
    2.     Pin Functions—DRV8910-Q1
    3.     Pin Functions—DRV8908-Q1
    4.     Pin Functions—DRV8906-Q1
    5.     Pin Functions—DRV8904-Q1
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Half Bridge Drivers
        1. 8.3.1.1 Control Modes
          1. 8.3.1.1.1 Continuous Mode (Without PWM)
          2. 8.3.1.1.2 Chopping Mode (With PWM)
            1. 8.3.1.1.2.1 PWM Configuration
            2. 8.3.1.1.2.2 Free-Wheeling Mode (Synchronous Rectification) Disable / Enable
            3. 8.3.1.1.2.3 PWM Channels Mapping
            4. 8.3.1.1.2.4 PWM Channels Configuration (PWM Frequency and PWM Duty)
            5. 8.3.1.1.2.5 Half-Bridge Enable
          3. 8.3.1.1.3 Parallel Mode (Continuous Operation)
          4. 8.3.1.1.4 Parallel Mode (PWM Operation)
            1. 8.3.1.1.4.1 PWM Configuration
            2. 8.3.1.1.4.2 Free-Wheeling Mode (Synchronous Rectification) Disable / Enable
            3. 8.3.1.1.4.3 PWM Channels Mapping
            4. 8.3.1.1.4.4 PWM Channels Configuration (PWM Frequency and PWM Duty)
            5. 8.3.1.1.4.5 PWM Generators Disable
            6. 8.3.1.1.4.6 Half-Bridge Enable
            7. 8.3.1.1.4.7 PWM Generators Enable
        2. 8.3.1.2 Half-Bridge Drive Architecture
          1. 8.3.1.2.1 Slew Rate
          2. 8.3.1.2.2 Cross Conduction (Dead Time)
          3. 8.3.1.2.3 Propagation Delay
      2. 8.3.2 Pin Diagrams
        1. 8.3.2.1 Logic Level Input Pin (nSLEEP, SCLK and SDI)
        2. 8.3.2.2 Logic Level Input Pin (nSCS)
        3. 8.3.2.3 Open Drain Output Pin (nFAULT)
        4. 8.3.2.4 Push Pull Output Pin (SDO)
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 VM Supply Undervoltage Lockout (UVLO)
        2. 8.3.3.2 VM Supply Overvoltage Protection (OVP)
        3. 8.3.3.3 Logic Supply Power on Reset (POR)
        4. 8.3.3.4 Overcurrent Protection (OCP)
        5. 8.3.3.5 Open-load detection (OLD)
          1. 8.3.3.5.1 Active OLD
            1. 8.3.3.5.1.1 Negative-current OLD
          2. 8.3.3.5.2 Low-current OLD
          3. 8.3.3.5.3 Passive OLD
        6. 8.3.3.6 Thermal Warning (OTW)
        7. 8.3.3.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode (nSLEEP = 0)
      2. 8.4.2 Operating Mode (nSLEEP = 1)
      3. 8.4.3 Fault Mode
    5. 8.5 Programming
      1. 8.5.1 SPI
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Map
      1. 8.6.1 DRV8912-Q1 and DRV8910-Q1 Register Maps
        1. 8.6.1.1 Status Registers
          1. 8.6.1.1.1 IC Status (IC_STAT) Register (Address = 0x00) [reset = 0x00]
            1. Table 20. IC Status Register Field Descriptions
          2. 8.6.1.1.2 Overcurrent Protection (OCP) Status 1 (OCP_STAT_1) Register (Address = 0x01) [reset = 0x00]
            1. Table 21. Overcurrent Protection (OCP) Status 1 Register Field Descriptions
          3. 8.6.1.1.3 Overcurrent Protection (OCP) Status 2 (OCP_STAT_2) Register (Address = 0x02) [reset = 0x00]
            1. Table 22. Overcurrent Protection (OCP) Status 2 Register Field Descriptions
          4. 8.6.1.1.4 Overcurrent Protection (OCP) Status 3 (OCP_STAT_3) Register (Address = 0x03) [reset = 0x00]
            1. Table 23. Overcurrent Protection (OCP) Status 3 Register Field Descriptions
          5. 8.6.1.1.5 Open-Load Detect (OLD) Status 1 (OLD_STAT_1) Register (Address = 0x04) [reset = 0x00]
            1. Table 24. Open-Load Detect (OLD) Status 1 Register Field Descriptions
          6. 8.6.1.1.6 Open-Load Detect (OLD) Status 2 (OLD_STAT_2) Register (Address = 0x05) [reset = 0x00]
            1. Table 25. Open-Load Detect (OLD) Status 2 Register Field Descriptions
          7. 8.6.1.1.7 Open-Load Detect (OLD) Status 3 (OLD_STAT_3) Register (Address = 0x06) [reset = 0x00]
            1. Table 26. Open-Load Detect (OLD) Status 3 Register Field Descriptions
        2. 8.6.1.2 Control Registers
          1. 8.6.1.2.1  Configuration (CONFIG_CTRL) Register (Address = 0x07) [reset = 0x00]
            1. Table 28. Configuration Register Field Descriptions
          2. 8.6.1.2.2  Operation Control 1 (OP_CTRL_1) Register (Address = 0x08) [reset = 0x00]
            1. Table 29. Operation Control 1 Register Field Descriptions
          3. 8.6.1.2.3  Operation Control 2 (OP_CTRL_2) Register (Address = 0x09) [reset = 0x00]
            1. Table 30. Operation Control 2 Register Field Descriptions
          4. 8.6.1.2.4  Operation Control 3 (OP_CTRL_3) Register (Address = 0x0A) [reset = 0x00]
            1. Table 31. Operation Control 3 Register Field Descriptions
          5. 8.6.1.2.5  PWM Control 1 (PWM_CTRL_1) Register (Address = 0x0B) [reset = 0x00]
            1. Table 32. PWM Control 1 Register Field Descriptions
          6. 8.6.1.2.6  PWM Control 2 (PWM_CTRL_2) Register (Address = 0x0C) [reset = 0x00]
            1. Table 33. PWM Control 2 Register Field Descriptions
          7. 8.6.1.2.7  Free-Wheeling Control 1 (FW_CTRL_1) Register (Address = 0x0D) [reset = 0x00]
            1. Table 34. Free-Wheeling Control 1 Register Field Descriptions
          8. 8.6.1.2.8  Free-Wheeling Control 2 (FW_CTRL_2) Register (Address = 0x0E) [reset = 0x00]
            1. Table 35. Free-Wheeling Control 2 Register Field Descriptions
          9. 8.6.1.2.9  PWM Map Control 1 (PWM_MAP_CTRL_1) Register (Address = 0x0F) [reset = 0x00]
            1. Table 36. PWM Map Control 1 Register Field Descriptions
          10. 8.6.1.2.10 PWM Map Control 2 (PWM_MAP_CTRL_2) Register (Address = 0x10) [reset = 0x00]
            1. Table 37. PWM Map Control 2 Register Field Descriptions
          11. 8.6.1.2.11 PWM Map Control 3 (PWM_MAP_CTRL_3) Register (Address = 0x11) [reset = 0x00]
            1. Table 38. PWM Map Control 3 Register Field Descriptions
          12. 8.6.1.2.12 PWM Frequency Control (PWM_FREQ_CTRL) Register (Address = 0x12) [reset = 0x00]
            1. Table 39. PWM Frequency Control Register Field Descriptions
          13. 8.6.1.2.13 PWM Duty Control Channel 1 (PWM_DUTY_CH1) Register (Address = 0x13) [reset = 0x00]
            1. Table 40. PWM Duty Control Channel 1 Register Field Descriptions
          14. 8.6.1.2.14 PWM Duty Control Channel 2 (PWM_DUTY_CH2) Register (Address = 0x14) [reset = 0x00]
            1. Table 41. PWM Duty Control Channel 2 Register Field Descriptions
          15. 8.6.1.2.15 PWM Duty Control Channel 3 (PWM_DUTY_CH3) Register (Address = 0x15) [reset = 0x00]
            1. Table 42. PWM Duty Control Channel 3 Register Field Descriptions
          16. 8.6.1.2.16 PWM Duty Control Channel 4 (PWM_DUTY_CH4) Register (Address = 0x16) [reset = 0x00]
            1. Table 43. PWM Duty Control Channel 4 Register Field Descriptions
          17. 8.6.1.2.17 Slew Rate Control 1 (SR_CTRL_1) Register (Address = 0x17) [reset = 0x00]
            1. Table 44. Slew Rate Control 1 Register Field Descriptions
          18. 8.6.1.2.18 Slew Rate Control 2 (SR_CTRL_2) Register (Address = 0x18) [reset = 0x00]
            1. Table 45. Slew Rate Control 2 Register Field Descriptions
          19. 8.6.1.2.19 Open-Load Detect (OLD) Control 1 (OLD_CTRL_1) Register (Address = 0x19) [reset = 0x00]
            1. Table 46. Open-Load Detect (OLD) Control (OLD_CTRL_1) Register Field Descriptions
          20. 8.6.1.2.20 Open-Load Detect (OLD) Control 2 (OLD_CTRL_2) Register (Address = 0x1A) [reset = 0x00]
            1. Table 47. Open-Load Detect (OLD) Control (OLD_CTRL_2) Register Field Descriptions
          21. 8.6.1.2.21 Open-Load Detect (OLD) Control 3 (OLD_CTRL_3) Register (Address = 0x1B) [reset = 0x00]
            1. Table 48. Open-Load Detect (OLD) Control (OLD_CTRL_3) Register Field Descriptions
          22. 8.6.1.2.22 Open-Load Detect (OLD) Control 4 (OLD_CTRL_4) Register (Address = 0x24) [reset = 0x00]
            1. Table 49. Open-Load Detect (OLD) Control (OLD_CTRL_4) Register Field Descriptions
      2. 8.6.2 DRV8908-Q1, DRV8906-Q1 and DRV8904-Q1 Register Maps
        1. 8.6.2.1 Status Registers
          1. 8.6.2.1.1 IC Status (IC_STAT) Register (Address = 0x00) [reset = 0x00]
            1. Table 54. IC Status Register Field Descriptions
          2. 8.6.2.1.2 Overcurrent Protection (OCP) Status 1 (OCP_STAT_1) Register (Address = 0x01) [reset = 0x00]
            1. Table 55. Overcurrent Protection (OCP) Status 1 Register Field Descriptions
          3. 8.6.2.1.3 Overcurrent Protection (OCP) Status 2 (OCP_STAT_2) Register (Address = 0x02) [reset = 0x00]
            1. Table 56. Overcurrent Protection (OCP) Status 2 Register Field Descriptions
          4. 8.6.2.1.4 Overcurrent Protection (OCP) Status 3 (OCP_STAT_3) Register (Address = 0x03) [reset = 0x00]
            1. Table 57. Overcurrent Protection (OCP) Status 3 Register Field Descriptions
          5. 8.6.2.1.5 Open-Load Detect (OLD) Status 1 (OLD_STAT_1) Register (Address = 0x04) [reset = 0x00]
            1. Table 58. Open-Load Detect (OLD) Status 1 Register Field Descriptions
          6. 8.6.2.1.6 Open-Load Detect (OLD) Status 2 (OLD_STAT_2) Register (Address = 0x05) [reset = 0x00]
            1. Table 59. Open-Load Detect (OLD) Status 2 Register Field Descriptions
          7. 8.6.2.1.7 Open-Load Detect (OLD) Status 3 (OLD_STAT_3) Register (Address = 0x06) [reset = 0x00]
            1. Table 60. Open-Load Detect (OLD) Status 3 Register Field Descriptions
        2. 8.6.2.2 Control Registers
          1. 8.6.2.2.1  Configuration (CONFIG_CTRL) Register (Address = 0x07) [reset = 0x00]
            1. Table 62. Configuration Register Field Descriptions
          2. 8.6.2.2.2  Operation Control 1 (OP_CTRL_1) Register (Address = 0x08) [reset = 0x00]
            1. Table 63. Operation Control 1 Register Field Descriptions
          3. 8.6.2.2.3  Operation Control 2 (OP_CTRL_2) Register (Address = 0x09) [reset = 0x00]
            1. Table 64. Operation Control 2 Register Field Descriptions
          4. 8.6.2.2.4  Operation Control 3 (OP_CTRL_3) Register (Address = 0x0A) [reset = 0x00]
            1. Table 65. Operation Control 3 Register Field Descriptions
          5. 8.6.2.2.5  PWM Control 1 (PWM_CTRL_1) Register (Address = 0x0B) [reset = 0x00]
            1. Table 66. PWM Control 1 Register Field Descriptions
          6. 8.6.2.2.6  PWM Control 2 (PWM_CTRL_2) Register (Address = 0x0C) [reset = 0x00]
            1. Table 67. PWM Control 2 Register Field Descriptions
          7. 8.6.2.2.7  Free-Wheeling Control 1 (FW_CTRL_1) Register (Address = 0x0D) [reset = 0x00]
            1. Table 68. Free-Wheeling Control 1 Register Field Descriptions
          8. 8.6.2.2.8  Free-Wheeling Control 2 (FW_CTRL_2) Register (Address = 0x0E) [reset = 0x00]
            1. Table 69. Free-Wheeling Control 2 Register Field Descriptions
          9. 8.6.2.2.9  PWM Map Control 1 (PWM_MAP_CTRL_1) Register (Address = 0x0F) [reset = 0x00]
            1. Table 70. PWM Map Control 1 Register Field Descriptions
          10. 8.6.2.2.10 PWM Map Control 2 (PWM_MAP_CTRL_2) Register (Address = 0x10) [reset = 0x00]
            1. Table 71. PWM Map Control 2 Register Field Descriptions
          11. 8.6.2.2.11 PWM Map Control 3 (PWM_MAP_CTRL_3) Register (Address = 0x11) [reset = 0x00]
            1. Table 72. PWM Map Control 3 Register Field Descriptions
          12. 8.6.2.2.12 PWM Map Control 4 (PWM_MAP_CTRL_4) Register (Address = 0x12) [reset = 0x00]
            1. Table 73. PWM Map Control 4 Register Field Descriptions
          13. 8.6.2.2.13 PWM Frequency Control 1 (PWM_FREQ_CTRL_1) Register (Address = 0x13 [reset = 0x00]
            1. Table 74. PWM Frequency Control 1 Register Field Descriptions
          14. 8.6.2.2.14 PWM Frequency Control 2 (PWM_FREQ_CTRL_2) Register (Address = 0x14 [reset = 0x00]
            1. Table 75. PWM Frequency Control 2 Register Field Descriptions
          15. 8.6.2.2.15 PWM Duty Control Channel 1 (PWM_DUTY_CH1) Register (Address = 0x15) [reset = 0x00]
            1. Table 76. PWM Duty Control Channel 1 Register Field Descriptions
          16. 8.6.2.2.16 PWM Duty Control Channel 2 (PWM_DUTY_CH2) Register (Address = 0x16) [reset = 0x00]
            1. Table 77. PWM Duty Control Channel 2 Register Field Descriptions
          17. 8.6.2.2.17 PWM Duty Control Channel 3 (PWM_DUTY_CH3) Register (Address = 0x17) [reset = 0x00]
            1. Table 78. PWM Duty Control Channel 3 Register Field Descriptions
          18. 8.6.2.2.18 PWM Duty Control Channel 4 (PWM_DUTY_CH4) Register (Address = 0x18) [reset = 0x00]
            1. Table 79. PWM Duty Control Channel 4 Register Field Descriptions
          19. 8.6.2.2.19 PWM Duty Control Channel 5 (PWM_DUTY_CH5) Register (Address = 0x19) [reset = 0x00]
            1. Table 80. PWM Duty Control Channel 5 Register Field Descriptions
          20. 8.6.2.2.20 PWM Duty Control Channel 6 (PWM_DUTY_CH6) Register (Address = 0x1A) [reset = 0x00]
            1. Table 81. PWM Duty Control Channel 6 Register Field Descriptions
          21. 8.6.2.2.21 PWM Duty Control Channel 7 (PWM_DUTY_CH7) Register (Address = 0x1B) [reset = 0x00]
            1. Table 82. PWM Duty Control Channel 7 Register Field Descriptions
          22. 8.6.2.2.22 PWM Duty Control Channel 8 (PWM_DUTY_CH8) Register (Address = 0x1C) [reset = 0x00]
            1. Table 83. PWM Duty Control Channel 8 Register Field Descriptions
          23. 8.6.2.2.23 Slew Rate Control 1 (SR_CTRL_1) Register (Address = 0x1D [reset = 0x00]
            1. Table 84. Slew Rate Control 1 Register Field Descriptions
          24. 8.6.2.2.24 Slew Rate Control 2 (SR_CTRL_2) Register (Address = 0x1E) [reset = 0x00]
            1. Table 85. Slew Rate Control 2 Register Field Descriptions
          25. 8.6.2.2.25 Open-Load Detect (OLD) Control 1 (OLD_CTRL_1) Register (Address = 0x1F) [reset = 0x00]
            1. Table 86. Open-Load Detect (OLD) Control (OLD_CTRL_1) Register Field Descriptions
          26. 8.6.2.2.26 Open-Load Detect (OLD) Control 2 (OLD_CTRL_2) Register (Address = 0x20) [reset = 0x00]
            1. Table 87. Open-Load Detect (OLD) Control (OLD_CTRL_2) Register Field Descriptions
          27. 8.6.2.2.27 Open-Load Detect (OLD) Control 3 (OLD_CTRL_3) Register (Address = 0x21) [reset = 0x00]
            1. Table 88. Open-Load Detect (OLD) Control (OLD_CTRL_3) Register Field Descriptions
          28. 8.6.2.2.28 Open Load Detect (OLD) Control 4 (OLD_CTRL_4) Register (Address = 0x22) [reset = 0x00]
            1. Table 89. Open Load Detect (OLD) Control (OLD_CTRL_4) Register Field Descriptions
          29. 8.6.2.2.29 Open Load Detect (OLD) Control 5 (OLD_CTRL_5) Register (Address = 0x23) [reset = 0x00]
            1. Table 90. Open Load Detect (OLD) Control (OLD_CTRL_5) Register Field Descriptions
          30. 8.6.2.2.30 Open Load Detect (OLD) Control 6 (OLD_CTRL_6) Register (Address = 0x24) [reset = 0x00]
            1. Table 91. Open Load Detect (OLD) Control (OLD_CTRL_6) Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Current Rating
          2. 9.2.1.2.2 Power Dissipation
      2. 9.2.2 Alternative Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 H-Bridge Requirements for Parallel Operation
      3. 9.2.3 Application Curves
    3. 9.3 Thermal Application
      1. 9.3.1 Power Dissipation
        1. 9.3.1.1 Power Dissipation Due to Device On-State Resistance (RDS(ON))
        2. 9.3.1.2 Power Dissipation Due to Switching Losses
        3. 9.3.1.3 Power Dissipation Due to Quiescent Current
        4. 9.3.1.4 Total Power Dissipation
      2. 9.3.2 PCB Types
      3. 9.3.3 Thermal Parameters
      4. 9.3.4 Transient Thermal
      5. 9.3.5 Device Junction Temperature Estimation
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1.1.1 Continuous Mode (Without PWM)

The half-bridges are configured to operate in the continuous mode without using any PWM switching by default. Any high-side or low-side switch is switched on by individually setting the high-side enable bits (HBX_HS_EN) and low-side enable bits (HBX_LS_EN) in operation control registers (OP_CTRL_1, OP_CTRL_2 and OP_CTRL_3).

NOTE

If the high-side enable bit (HBX_HS_EN) and low-side enable bit (HBX_LS_EN) of a particular half-bridge is set high (shoot-through configuration), then the particular half-bridge driver will remain in Hi-Z state until he shoot-through condition is cleared.

The high-side and low-side enable bits of a particular half-bridge are configured to drive the motor in forward mode, reverse mode, brake mode and coast mode as shown in Table 2.

Table 2. Motor Operation in Continuous Mode (Motor Connected between HB1 and HB2)

nSLEEP HALF-BRIDGE-1 HALF-BRIDGE-2 OUT1 OUT2 BRIDGE OPERATION
(DC MOTOR)
0 HB1_HS_EN = Don't Care
HB1_LS_EN = Don't Care		 HB2_HS_EN = Don't Care
HB2_LS_EN = Don't Care 		Z Z Sleep Mode
1 HB1_HS_EN = 0
HB1_LS_EN = 0		 HB2_HS_EN = 0
HB2_LS_EN = 0 		Z Z Motor Coast
1 HB1_HS_EN = 1
HB1_LS_EN = 0		 HB2_HS_EN = 0
HB2_LS_EN = 1 		H L Forward Direction
1 HB1_HS_EN = 0
HB1_LS_EN = 1		 HB2_HS_EN = 1
HB2_LS_EN = 0 		L H Reverse Direction
1 HB1_HS_EN = 0
HB1_LS_EN =1		 HB2_HS_EN = 0
HB2_LS_EN = 1 		L L Motor Brake (Low-Side)
1 HB1_HS_EN =1
HB1_LS_EN = 0		 HB2_HS_EN = 1
HB2_LS_EN = 0 		H H Motor Brake (High-Side)
1 HB1_HS_EN = 1
HB1_LS_EN = 1		 HB2_HS_EN = 1
HB2_LS_EN = 1 		Z Z Motor Coast

Figure 24 shows the bridge configuration for motor operation in forward direction with high-side FET of OUT1 and low-side FET of OUT2 in conducting state with current flowing from OUT1 to OUT2. Similarly, the motor operation in reverse direction is achieved by switching ON the high-side FET of OUT2 and low-side FET of OUT1 such that current flows from OUT2 to OUT1 as shown in Figure 25.

DRV8904-Q1 DRV8906-Q1 DRV8908-Q1 DRV8910-Q1 DRV8912-Q1 drv89xx-continuous-mode-FW.gifFigure 24. Continuous Mode (Forward Direction)
DRV8904-Q1 DRV8906-Q1 DRV8908-Q1 DRV8910-Q1 DRV8912-Q1 drv89xx-continuous-mode-RW.gifFigure 25. Continuous Mode (Reverse Direction)

Figure 26 and Figure 27 shows the bridge operation in coast mode with motor initially running in forward and reverse direction respectively. As shown in these figures, due to the energy stored in motor's inductance, the current will continue to flow in motor and take the path flow through the body diodes of FETs.

DRV8904-Q1 DRV8906-Q1 DRV8908-Q1 DRV8910-Q1 DRV8912-Q1 drv89xx-continuous-coast.gifFigure 26. Continuous Mode (Coast - From Forward Direction)
DRV8904-Q1 DRV8906-Q1 DRV8908-Q1 DRV8910-Q1 DRV8912-Q1 drv89xx-continuous-coast-1.gifFigure 27. Continuous Mode (Coast- From Reverse Direction)

Figure 28 shows the low-side braking of the motor when both low-side FET's of the driver are turned ON. In this case, the motor is considered to be operating in forward direction (current flow from OUT1 to OUT2) and then braking is applied. similarly, for the high-side braking, both high-side FET's of the driver are turned ON as shown in Figure 29.

DRV8904-Q1 DRV8906-Q1 DRV8908-Q1 DRV8910-Q1 DRV8912-Q1 drv89xx-continuous-brake.gifFigure 28. Continuous Mode (Brake - Low-Side)
DRV8904-Q1 DRV8906-Q1 DRV8908-Q1 DRV8910-Q1 DRV8912-Q1 drv89xx-continuous-brake-1.gifFigure 29. Continuous Mode (Brake - High-Side)