JAJSGV8B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The synchronous rectification of the half-bridge operating in PWM can be enabled by setting the HBX_FW bit in free-wheeling control registers (FW_CTRL_1 and FW_CTRL_2). Figure 30 shows the operation of the driver when the synchronous rectification mode is disabled. As shown in this figure, during the PWM off time, the high-side diode of the OUT2 conducts to close the current path required for motor.
When synchronous rectification mode is enabled, if either of the low-side or high-side of the half-bridge operates in the PWM switching, then the other switch of the same half-bridge operates in complementary fashion. Figure 31 shows such example of the synchronous rectification, where the high-side FET of OUT2 half-bridge is turned ON when the low-side FET of same half-bridge is turned off in a PWM cycle.
NOTE
The default mode of any half-bridge is asynchronous rectification mode. If the corresponding bit in FW_CTRL_X regsiter is not set, then the particular half-bridge will operate in asynchronous rectification mode.