JAJSGV8B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
When the nSLEEP pin is high and VVM > VUVLO, the device enters operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the half bridge drivers, charge pump, internal regulators, and SPI bus are active. Table 11 summarizes the different operating modes of DRV89XX-Q1 device.
MODE | CONDITION | HALF-BRIDGES | INTERNAL CIRCUITS |
---|---|---|---|
Operating | 4.5-V < VVM < 20-V (EXT_OVP = 0b)
4.5-V < VVM < 32-V (EXT_OVP = 1b) nSLEEP Pin = High |
Operating | Operating |
Sleep | 4.5-V < VVM < 32-V
nSLEEP Pin = Low |
Disabled | Disabled |
Fault | Any Fault Condition Met | Depends on Fault | Depends on Fault |