JAJSGV8B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The low-side FET's of half-bridges OUT4, OUT5 and OUT6 are mapped to any of the PWM generator by using the HBX_PWM_MAP bits in PWM mapping control registers. For parallel operation, all the half-bridges operating in PWM mode is mapped to a single PWM generator. Considering that PWM generator-4 is used for the mapping of half-bridges, following bits of the PWM_MAP_CTRL_X registers are affected:
NOTE
If the PWM of any channel is enabled, then it is mapped to PWM generator-1 by default.