JAJSG74C February   2012  – September 2018 DS90C187

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
      2.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     DS90C187 Pin Descriptions — Serializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Input Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 AC Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Device Functional Modes
      1. 8.3.1  Device Configuration
      2. 8.3.2  Single Pixel Input / Single Pixel Output
      3. 8.3.3  Single Pixel Input / Dual Pixel Output
      4. 8.3.4  Dual Pixel Input / Dual Pixel Output
      5. 8.3.5  Pixel Clock Edge Select (RFB)
      6. 8.3.6  Power Management
      7. 8.3.7  Sleep Mode (PDB)
      8. 8.3.8  LVDS Outputs
      9. 8.3.9  18 bit / 24 bit Color Mode (18B)
      10. 8.3.10 LVCMOS Inputs
    4. 8.4 Programming
      1. 8.4.1 LVDS Interface / TFT Color Data Recommended Mapping
        1. 8.4.1.1 Color Mapping Information
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LVDS Interconnect Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Sequence
    2. 10.2 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER MIN TYP MAX UNIT
TSTC INn_x Setup to IN_CLK See Figure 6 0 ns
THTC INn_x Hold from IN_CLK See Figure 6 2.5 ns
LLHT LVDS Low-to-High Transition Time
Figure 4(1) 		0.18 0.5 ns
LHLT LVDS High-to-Low Transition Time
Figure 4(1) 		0.18 0.5 ns
TBIT LVDS Output Bit Width MODE[1:0] = 00, or 10 1/7 TCIP ns
MODE[1:0] = 01 2/7 TCIP ns
TPPOS0 Transmitter Output Pulse Positions Normalized for Bit 0 See Figure 9 1 UI
TPPOS1 Transmitter Output Pulse Positions Normalized for Bit 1 See Figure 9 2 UI
TPPOS2 Transmitter Output Pulse Positions Normalized for Bit 2 See Figure 9 3 UI
TPPOS3 Transmitter Output Pulse Positions Normalized for Bit 3 See Figure 9 4 UI
TPPOS4 Transmitter Output Pulse Positions Normalized for Bit 4 See Figure 9 5 UI
TPPOS5 Transmitter Output Pulse Positions Normalized for Bit 5 See Figure 9 6 UI
TPPOS6 Transmitter Output Pulse Positions Normalized for Bit 6 See Figure 9 7 UI
ΔTPPOS Variation in Transmitter Pulse Position (Bit 6 — Bit 0) See Figure 9 ±0.06 UI
TCCS LVDS Channel to Channel Skew 110 ps
TJCC Jitter Cycle-to-Cycle MODE0, MODE1 = 0,
f = 105 MHz,
(1) 		0.028 0.035 UI
TPLLS Phase Lock Loop Set (Enable Time) Figure 7 1 ms
TPDD Powerdown Delay Figure 8
(2) 		100 ns
TSD Latency Delay MODE0 = 0,
MODE1 = 1 or 0
Figure 10
(1) 		2*TCIP + 10.54 2*TCIP + 13.96 ns
TLAT Latency Delay for Single Pixel In / Dual Pixel Out Mode MODE0 = 1,
MODE1 = 0
Figure 10
(1) 		9*TCIP + 4.19 9*TCIP + 6.36 ns
(1) Parameter is ensured by characterization and is not tested at final test.
(2) Parameter is ensured by design and is not tested at final test.