JAJS673J November   1999  – May 2016 DS90CF366 , DS90CF386

PRODUCTION DATA.  

1. 1 特長
2. 2 アプリケーション
3. 3 概要
4. 4 改訂履歴
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Switching Characteristics
   7. 6.7 Timing Diagrams
   8. 6.8 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagrams
   3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
         1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
   4. 7.4 Device Functional Modes
      1. 7.4.1 Power Sequencing and Power-Down Mode
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 Cables
         2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
         3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
         4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
9. 9 Power Supply Recommendations
10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
       1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
12. 12メカニカル、パッケージ、および注文情報