JAJS673J November   1999  – May 2016 DS90CF366 , DS90CF386

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Sequencing and Power-Down Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Cables
        2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
        3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
        4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DGG Package
48-Pin TSSOP
Top View
DGG Package
56-Pin TSSOP
Top View
NZC Package
64-Pin NFBGA
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME DS90CF366 DS90CF386
TSSOP TSSOP NFBGA
GND 3, 25, 32,
38, 44		 4, 28, 36,
44, 52		 A4, B1, B6,
D8, E3		 G Ground pins for LVCMOS outputs.
LVDS GND 7, 13, 18 8, 14, 21 E5, G3, G7, H5 G Ground pins for LVDS inputs.
LVDS VCC 12 13 E4, H4 P Power supply pin for LVDS inputs.
NC 6 — B2, C2, C7,
F3, F8, G2		 — Pins not connected.
PLL GND 19, 21 22, 24 F6, G8 G Ground pin for PLL.
PLL VCC 20 23 F7 P Power supply for PLL.
PWR DWN 22 25 E6 I LVCMOS level input. When asserted (low input) the receiver outputs are low.
RxCLKIN+ 17 18 H7 I Positive LVDS differential clock input.
RxCLKIN- 16 17 H6 I Negative LVDS differential clock input.
RxCLKOUT 23 26 E7 O LVCMOS level clock output. The falling edge acts as data strobe.
RxIN0+ 9 10 H3 I Positive LVDS differential data inputs.
RxIN0- 8 9 H2 I Negative LVDS differential data inputs.
RxIN1+ 11 12 G4 I Positive LVDS differential data inputs.
RxIN1- 10 11 F4 I Negative LVDS differential data inputs.
RxIN2+ 15 16 F5 I Positive LVDS differential data inputs.
RxIN2- 14 15 G5 I Negative LVDS differential data inputs.
RxIN3+ — 20 H8 I Positive LVDS differential data inputs.
RxIN3- — 19 G6 I Negative LVDS differential data inputs.
RxOUT0 24 27 E8 O LVCMOS level data output.
RxOUT1 26 29 C8 O LVCMOS level data output.
RxOUT2 27 30 D7 O LVCMOS level data output.
RxOUT3 29 32 B8 O LVCMOS level data output.
RxOUT4 30 33 C6 O LVCMOS level data output.
RxOUT5 31 34 B7 O LVCMOS level data output.
RxOUT6 33 35 A8 O LVCMOS level data output.
RxOUT7 34 37 A7 O LVCMOS level data output.
RxOUT8 35 38 A6 O LVCMOS level data output.
RxOUT9 37 39 C5 O LVCMOS level data output.
RxOUT10 39 41 D5 O LVCMOS level data output.
RxOUT11 40 42 B4 O LVCMOS level data output.
RxOUT12 41 43 A5 O LVCMOS level data output.
RxOUT13 43 45 D4 O LVCMOS level data output.
RxOUT14 45 46 C4 O LVCMOS level data output.
RxOUT15 46 47 A3 O LVCMOS level data output.
RxOUT16 47 49 B3 O LVCMOS level data output.
RxOUT17 1 50 A1 O LVCMOS level data output.
RxOUT18 2 51 C3 O LVCMOS level data output.
RxOUT19 4 53 D3 O LVCMOS level data output.
RxOUT20 5 54 D2 O LVCMOS level data output.
RxOUT21 — 55 C1 O LVCMOS level data output.
RxOUT22 — 1 E1 O LVCMOS level data output.
RxOUT23 — 2 F1 O LVCMOS level data output.
RxOUT24 — 3 E2 O LVCMOS level data output.
RxOUT25 — 5 G1 O LVCMOS level data output.
RxOUT26 — 6 F2 O LVCMOS level data output.
RxOUT27 — 7 H1 O LVCMOS level data output.
VCC 28, 36, 42, 48 31, 40, 48, 56 A2, B5, D1, D6 P Power supply pins for LVCMOS outputs.
(1) G = Ground, I = Input, O = Output, and P = Power