JAJSEP1A February   2018  – March 2018 ESD224

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings -JEDEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Setup
    1. 7.1 IEC 61000-4-2 System Level ESD Test Setup with HDMI Driver for Clamping Voltage Measurement
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 IEC 61000-4-2 ESD Protection
      2. 8.3.2 IEC 61000-4-4 EFT Protection
      3. 8.3.3 IEC 61000-4-5 Surge Protection
      4. 8.3.4 IO Capacitance
      5. 8.3.5 DC Breakdown Voltage
      6. 8.3.6 Ultra Low Leakage Current
      7. 8.3.7 Low ESD Clamping Voltage
      8. 8.3.8 Supports High Speed Interfaces
      9. 8.3.9 Industrial Temperature Range
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Signal Range
        2. 9.2.2.2 Operating Frequency
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA, across operating temperature range -3.6 3.6 V
VBRF Breakdown voltage, Pin 1, 2, 4, 5 to 3 (GND) (1) IIO = 1 mA 5 7.9 V
VBRR Reverse breakdown voltage, pin 1, 2, 4, 5 to 3 (GND) (1) IIO = -1 mA -7.9 -5 V
VHOLD Holding voltage, pin1, 2, 4, 5 to 3 (GND) and 3 (GND) to pin 1, 2, 4, 5 (2) IIO = 1 mA 6.3 V
VHOLD-NEG Breakdown voltage, pin1, 2, 4, 5 to 3 (GND)  (2) IIO = -1 mA -6.3 V
VCLAMP TLP Clamping voltage (Intrinsic) IPP = 1 A, pin 1, 2, 4, 5 to 3 or 8(GND), GND to pin 1, 2, 4, 5 7 V
IPP = 5 A, pin 1, 2, 4, 5 to 3 or 8(GND), GND to pin 1, 2, 4, 5 9 V
IPP = 16 A, pin 1, 2, 4, 5 to 3 or 8(GND), GND to pin 1, 2, 4, 5 14 V
VCLAMP-IEC-SYS IEC 61000-4-2 30 ns Clamping voltage (system side) assuming system draws at least 3 A of current at 8 V. See measurement setup. 8-kV Contact discharge on pin 1, 2, 4, 5 with pin3 grounded. Voltage waveform measured at pin 6, 7, 9, 10 with respect to GND 8 V
-8-kV Contact discharge on pin 1, 2, 4, 5 with pin3 grounded. Voltage waveform measured at pin 6, 7, 9, 10 with respect to GND -5 V
RDYN Dynamic resistance Pin 1, 2, 4, 5 to GND, 100 ns TLP 0.5 Ω
GND to Pin 1, 2, 4, 5 , 100 ns TLP 0.5
CLINE Line capacitance, any IO to GND VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.5 0.6 pF
ΔCLINE Variation of line capacitance CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.02 0.07 pF
CCROSS Line-to-line capacitnace between one differential pair to another differnetial pair VIO = 0 V, Vrms = 30 mV, f = 1 MHz 0.28 pF
S21DC DC Insertion Loss  DC insertion loss at Ch1, Ch2, Ch3, Ch4  0.3 dB
Ileakage Leakage Current VIO=±3.6 V, Pin 1,2,4,5 to Pin 3 0.1 10 nA
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.