SLLS629M January   2006  – October 2024 ISO721 , ISO721M , ISO722 , ISO722M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Safety Limiting Values
    7. 6.7  Insulation Specifications
    8. 6.8  Safety-Related Certifications
    9. 6.9  Electrical Characteristics, 5 V, 3.3 V
    10. 6.10 Electrical Characteristics, 5 V
    11. 6.11 Switching Characteristics, 3.3 V, 5 V
    12. 6.12 Electrical Characteristics, 3.3 V, 5 V
    13. 6.13 Electrical Characteristics, 3.3 V
    14. 6.14 Switching Characteristics, 3.3 V
    15. 6.15 Switching Characteristics, 5 V, 3.3 V
    16. 6.16 Switching Characteristics, 5 V
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
      1. 8.3.1 Device I/O Schematic
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Insulation Characteristics Curves
        2. 9.2.3.2 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 PCB Material
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.11 Switching Characteristics, 3.3 V, 5 V

VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay, low-to-high-level output ISO72x EN at 0 V,
See Figure 7-1		 12 17 30 ns
tPHL Propagation delay , high-to-low-level output 12 17 30 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 2 ns
tPLH Propagation delay, low-to-high-level output ISO72xM 10 12 21 ns
tPHL Propagation delay, high-to-low-level output 10 12 21 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 1 ns
tsk(pp)(1) Part-to-part skew 0 5 ns
tr Output signal rise time EN at 0 V,
See Figure 7-1		 2.3 ns
tf Output signal fall time 2.3 ns
tpHZ Sleep-mode propagation delay,
high-level-to-high-impedance output		 ISO722
ISO722M		 See Figure 7-2 5.4 9 15 ns
tpZH Sleep-mode propagation delay,
high-impedance-to-high-level output		 4.5 5 15 μs
tpLZ Sleep-mode propagation delay,
low-level-to-high-impedance output		 See Figure 7-3 5.4 9 15 ns
tpZL Sleep-mode propagation delay,
high-impedance-to-low-level output		 4.5 5 15 μs
tfs Failsafe output delay time from input power loss See Figure 7-4 3 μs
tjit(PP) Peak-to-peak eye-pattern jitter ISO72x 100-Mbps NRZ data input, See Figure 7-6 2 ns
100-Mbps unrestricted bit run length data input, See Figure 7-6 3
ISO72xM 150-Mbps NRZ data input, See Figure 7-6 1
150-Mbps unrestricted bit run length data input, See Figure 7-6 2
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.