SLLS629L January 2006 – October 2015 ISO721 , ISO721M , ISO722 , ISO722M
PRODUCTION DATA.
The isolator in the Functional Block Diagram is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, creating a sufficiently high-frequency signal capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing the carrier on to the output multiplexer.
Insulation characteristics and regulatory information of ISO72x family is provided in this section.
over recommended operating conditions (unless otherwise noted.)
PARAMETER | TEST CONDITIONS | SPECIFICATIONS | UNIT | |
---|---|---|---|---|
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(1) | ||||
VIORM | Maximum working insulation voltage | 560 | Vpeak | |
VPR | Input to output test voltage | After Input/Output Safety Test Subgroup 2/3 VPR = VIORM × 1.2, t = 10 s, Partial discharge < 5 pC |
672 | Vpeak |
Method a, VPR = VIORM × 1.6, Type and sample test with t = 10 s, Partial discharge < 5 pC |
896 | Vpeak | ||
Method b1, VPR = VIORM × 1.875, 100% production test with t = 1 s, Partial discharge < 5 pC |
1050 | Vpeak | ||
VIOTM | Transient overvoltage | t = 60 s | 4000 | Vpeak |
RS | Insulation resistance | VIO = 500 V at TS | > 109 | Ω |
Pollution degree | 2 | |||
UL 1577 | ||||
VISO | Isolation voltage | VTEST = VISO, t = 60 s (qualification) | 3535 / 2500 | Vpeak/Vrms |
VTEST = 1.2 × VISO, t = 1 s (100% production)(2) | 4242 / 3000 |
VDE | CSA | UL |
---|---|---|
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1) | Approved according to CSA Component Acceptance Notice 5A and IEC 60950-1 | Recognized under UL 1577 Component Recognition Program |
Basic Insulation Maximum Transient Overvoltage, 4000 VPK Maximum Working Voltage, 560 VPK Maximum Surge Voltage, 4000 VPK |
Evaluated to CSA 60950-1-07 and IEC 60950-1 (2nd Ed) with 2000 VRMS Isolation rating for products with working voltages ≤ 125 VRMS for reinforced insulation and ≤ 390 VRMS for basic insulation | Single Protection, 2500 VRMS(1) |
Certificate number: 40016131 | Master contract number: 220991 | File number: E181974 |
PARAMETER | DESCRIPTIONS / TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
L(101) | Minimum air gap (clearance)(1) | Shortest terminal-to-terminal distance through air | D-8 | 4 | mm | ||
DUB-8 | 6.1 | ||||||
L(102) | Minimum external tracking (creepage)(1) | Shortest terminal-to-terminal distance across the package surface | D-8 | 4 | mm | ||
DUB-8 | 6.8 | ||||||
CTI | Tracking resistance (comparative tracking index) | DIN EN 60112 (VDE 0303-11); IEC 60112 | 400 | V | |||
DTI | Distance through insulation | Minimum internal gap (internal clearance) | 0.008 | mm | |||
RIO | Isolation resistance | Input to output, VIO = 500 V; all pins on each side of the barrier tied together, creating a two-terminal device; TA = 25°C | 1012 | Ω | |||
Input to output, VIO = 500 V, 100°C ≤ TA< TA max. |
1011 | Ω | |||||
CIO | Barrier capacitance Input-to-output |
VI = 0.4 sin (4 × 106πt) | 1 | pF |
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply, and without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IS | Safety input, output, or supply current | θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C | 100 | mA | ||
θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C | 153 | |||||
TS | Maximum case temperature | 150 | °C |
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative.
Functional modes of ISO72x are shown in Table 1 and Table 2.
VCC1 | VCC2 | INPUT (IN) |
OUTPUT (OUT) |
---|---|---|---|
PU | PU | H | H |
L | L | ||
Open | H | ||
PD | PU | X | H |
X | PD | X | Undetermined |
VCC1 | VCC2 | INPUT (IN) |
OUTPUT ENABLE (EN) |
OUTPUT (OUT) |
---|---|---|---|---|
PU | PU | H | L or open | H |
L | L or open | L | ||
X | H | Z | ||
Open | L or open | H | ||
PD | PU | X | L or open | H |
PD | PU | X | H | Z |
X | PD | X | X | Undetermined |