JAJSLA3B May   2018  – October 2021 ISOW1412 , ISOW1432

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Recommended Operating Conditions
    3. 8.3  Thermal Information
    4. 8.4  Power Ratings
    5. 8.5  Insulation Specifications
    6. 8.6  Safety-Related Certifications
    7. 8.7  Safety Limiting Values
    8. 8.8  Electrical Characteristics
    9. 8.9  Supply Current Characteristics at VISOOUT = 3.3 V
    10. 8.10 Supply Current Characteristics at  VISOOUT = 5 V
    11. 8.11 Switching Characteristics at VISOOUT = 3.3 V
    12. 8.12 Switching Characteristics at VISOOUT = 5 V
    13. 8.13 Insulation Characteristics Curves
    14. 8.14 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Power Isolation
    3. 10.3 Signal Isolation
    4. 10.4 RS-485
    5. 10.5 Functional Block Diagram
    6. 10.6 Feature Description
      1. 10.6.1 Power-Up and Power-Down Behavior
      2. 10.6.2 Protection Features
      3. 10.6.3 Failsafe Receiver
      4. 10.6.4 Glitch-Free Power Up and Power Down
    7. 10.7 Device Functional Modes
    8. 10.8 Device I/O Schematics
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Data Rate, Bus Length and Bus Loading
        2. 11.2.2.2 Stub Length
        3. 11.2.2.3 Insulation Lifetime
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 サポート・リソース
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.7 Device Functional Modes

Table 10-1 lists the supply configuration for these devices:

Table 10-1 Supply configuration Function Table
INPUTS OUTPUT
VDD(1) VIO EN/FLT MODE VISOOUT(3)
< VDD(UVLO+) >VIO(UVLO+) H or Open X OFF
>VDD(UVLO+) <VIO(UVLO+) X Invalid Operation
5 V 1.71 V to 5.5 V High(shorted to VISOOUT) 5 V
5 V or 3.3 V 1.71 V to 5.5 V Low(shorted to GND2) or floating (2) 3.3 V
3.3 V 1.71 V to 5.5 V High(shorted to VISOOUT) Invalid Operation
X X L X OFF
(1) VDD= 3.3 V, MODE shorted to VISOOUT(essentially VISOOUT = 5 V) is an invalid operation
(2) The MODE pin has a weak pulldown internally. Therefore for VISOOUT = 3.3 V, the MODE pin should be strongly connected to the GND2 pin in noisy system scenarios.
(3) VISOOUT shorted to VISOIN on PCB. GND2 and GISOIN pins are shorted to each other and EN=High

Table 10-2 shows the driver functional modes:

Table 10-2 Driver Functional Table
INPUTS OUTPUTS(3)
VDD(1) VIO EN/FLT D DE Y, A Z, B
PU PU H or Open H H H L
L H L H
X L Hi-Z Hi-Z
X Open Hi-Z Hi-Z
Open H H L
L X X Hi-Z Hi-Z
PD PU X X X Hi-Z Hi-Z
PU PD(2) X X X Invalid Operation
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state
(2) A strongly driven input signal on D, DE or RE can weakly power the floating VIO through an internal protection diode and cause an undetermined output.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN=High

When the driver enable pin, DE, is logic high, the differential outputs, Y and Z, follow the logic states at data input, D. A logic high at the D input causes the Y output to go high and the Z output to go low. Therefore the differential output voltage defined by Equation 1 is positive.

Equation 1. VOD = VY – VZ

A logic low at the D input causes the Z output to go high and the Y output to go low. Therefore the differential output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when the DE pin is left open. The D pin has an internal pullup resistor. The Y output goes high and the Z output goes low when the D pin is left open while the driver enabled.

Table 10-3 shows the receiver functional modes:

Table 10-3 Receiver Functional Table
INPUTS OUTPUT
VDD(1) VIO EN/FLT Differential Input VID = VA- VB RE R (3)
PU PU H or Open VID > VIT+ L H
VIT- < VID < VIT+ L Indeterminate
VID < VIT- L L
X H Hi-Z
X Open Hi-Z
Open, Short, Idle L H
L X X H
PD PU X X X Hi-Z
PU PD(2) H or Open X X Invalid Operation
L X X
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state
(2) A strongly driven input signal on D, DE or RE can weakly power the floating VIO through an internal protection diode and cause an undetermined output.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN/FLT=High

The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+.

Equation 2. VID = VA – VB

The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the negative input threshold, VTH– . If the VID voltage is between the VTH+ and VTH– thresholds, the output is indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Other device feature functional states in shown in Table 10-4 and Table 10-5 below:

Table 10-4 DC-DC Converter Enable/Disable
INPUTS OUTPUT
VDDVIOEN/FLTVISOOUT
PUPUH or Open3.3 V or 5 V depending on MODE pin setting
PUPULOFF
Table 10-5 General Purpose Logic Input/Output
INPUTS OUTPUT Comments
VDD(1)(2) VIO EN/FLT IN OUT
PU PU H or Open H H Output channel assumes logic state governed by IN
L L
Open L Default state
L X Hi-Z Device is in disabled state when either of VDD or VIO is missing
PD PU X X Hi-Z
PU PD X X Invalid Operation
(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
(2) VISOOUT shorted to VISOIN on PCB. GISOIN and GND2 pins are shorted to each other and EN/FLT=High