8.2.2.8 Compensation Component Selection

The power stage transfer function of a voltage mode buck converter has a complex double pole related to the LC output filter and a left half plane zero due to the output capacitor ESR, denoted R_ESR. The locations of these singularities are given respectively in Equation 12.

Equation 12.

where

• C_O is the output capacitance value appropriately derated for applied voltage and operating temperature
• R_L is the effective load resistance
• R_DCR is the series damping resistance associated with the inductor and power switches

Figure 21. LM2854 Compensation Scheme

The conventional compensation strategy employed with voltage mode control is to use two compensator zeros to offset the LC double pole, one compensator pole located to cancel the output capacitor ESR zero and one compensator pole located between one third and one half switching frequency for high frequency noise attenuation.

The LM2854 internal compensation components are designed to locate a pole at the origin and a pole at high frequency as mentioned above. Furthermore, a zero is located at 8.8 kHz or 17.6 kHz for the 500 kHz or 1 MHz options, respectively, to approximately cancel the likely location of one LC filter pole.

The three external compensation components, R_FB1, R_COMP and C_COMP, are selected to position a zero at or below the LC pole location and a pole to cancel the ESR zero. The voltage loop crossover frequency, f_loop, is usually selected between one tenth to one fifth of the switching frequency, as shown in Equation 13.

A simple solution for the required external compensation capacitor, C_COMP, with type III voltage mode control can be expressed as in Equation 14.

Equation 14.

where the constant α is nominally 0.038 or 0.075 for the 500 kHz or 1 MHz options, respectively. This assumes a compensator pole cancels the output capacitor ESR zero. Furthermore, since the modulator gain is proportional to V_IN, the loop crossover frequency increases with V_IN. Thus, it is recommended to design the loop at maximum expected V_IN.

The upper feedback resistor, R_FB1, is selected to provide adequate mid-band gain and to locate a zero at or below the LC pole frequency. The series resistor, R_COMP, is selected to locate a pole at the ESR zero frequency, as shown in Equation 15.

Equation 15.

Note that the lower feedback resistor, R_FB2, has no impact on the control loop from an AC standpoint since the FB pin is the input to an error amplifier and effectively at AC ground. Hence, the control loop can be designed irrespective of output voltage level. The only caveat here is the necessary derating of the output capacitance with applied voltage. Having chosen R_FB1 as above, R_FB2 is then selected for the desired output voltage.

Table 1 and Table 2 list inductor and ranges of capacitor values that work well with the LM2854, along with the associated compensation components to ensure stable operation. Values different than those listed may be used, but the compensation components may need to be recalculated to avoid degradation in phase margin. Note that the capacitance ranges specified refer to in-circuit values where the nominal capacitance value is adequately derated for applied voltage.