LM3429/-Q1 N-Channel Controller for Constant Current LED Drivers

1 Features

LM3429-Q1 is AEC-Q100 Grade 1 Qualified for Automotive Applications
V_IN Range From 4.5 V to 75 V
Adjustable Current Sense Voltage
High-Side Current Sensing
2-Ω, 1-A Peak MosFET Gate Driver
Input Undervoltage Protection
Overvoltage Protection
PWM Dimming
Analog Dimming
Cycle-by-Cycle Current Limit
Programmable Switching Frequency
Low Profile 14-lead HTSSOP Package
Thermal Shutdown

2 Applications

LED Drivers - Buck, Boost, Buck-Boost, SEPIC
Indoor and Outdoor SSL
Automotive
General Illumination
Constant-Current Regulators

3 Description

The LM3429 is a versatile high voltage N-channel MosFET controller for LED drivers. It can be easily configured in buck, boost, buck-boost and SEPIC topologies. This flexibility, along with an input voltage rating of 75V, makes the LM3429 ideal for illuminating LEDs in a very diverse, large family of applications.

Adjustable high-side current sense voltage allows for tight regulation of the LED current with the highest efficiency possible. The LM3429 uses Predictive Off-time (PRO) control, which is a combination of peak current-mode control and a predictive off-timer. This method of control eases the design of loop compensation while providing inherent input voltage feed-forward compensation.

The LM3429 includes a high-voltage startup regulator that operates over a wide input range of 4.5 V to 75 V. The internal PWM controller is designed for adjustable switching frequencies of up to 2 MHz, thus enabling compact solutions. Additional features include analog dimming, PWM dimming, overvoltage protection, undervoltage lock-out, cycle-by-cycle current limit, and thermal shutdown.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LM3429	HTSSOP (14)	5.00 mm × 4.40 mm
LM3429-Q1	HTSSOP (14)	5.00 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Boost Application Circuit

4 Revision History

Changes from G Revision (April 2013) to H Revision

Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from F Revision (May 2013) to G Revision

Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

PWP Package

14- Pin HTSSOP

Top View

Pin Functions

PIN		I/O	DESCRIPTION	APPLICATION INFORMATION
NO.	NAME	I/O	DESCRIPTION	APPLICATION INFORMATION
1	V_IN	I	Input Voltage	Bypass with 100 nF capacitor to AGND as close to the device as possible in the circuit board layout.
2	COMP	I	Compensation	Connect a capacitor to AGND to set compensation.
3	CSH	I	Current Sense High	Connect a resistor to AGND to set signal current. For analog dimming, connect current source or potentiometer to AGND (see Analog Dimming section).
4	RCT	I	Resistor Capacitor Timing	Connect a resistor from the switch node and a capacitor to AGND to set the switching frequency.
5	AGND	GND	Analog Ground	Connect to PGND through the DAP copper circuit board pad to provide proper ground return for CSH, COMP, and RCT.
6	OVP	I	Overvoltage Protection	Connect to a resistor divider from the output (V_O) or the input to program output overvoltage lockout (OVLO). Turn-off threshold is 1.24 V and hysteresis for turn-on is provided by 20 µA current source.
7	nDIM	I	Not DIM input	Connect a PWM signal for dimming as detailed in the PWM Dimming section and/or a resistor divider from V_IN to program input undervoltage lockout (UVLO). Turn-on threshold is 1.24 V and hysteresis for turn-off is provided by 20 µA current source.
8	NC		No Connection	Leave open.
9	PGND	GND	Power Ground	Connect to AGND through DAP copper pad to provide ground return for GATE.
10	GATE	O	Gate Drive Output	Connect to the gate of the external NFET.
11	V_CC	I	Internal Regulator Output	Bypass with a 2.2 µF–3.3 µF, ceramic capacitor to PGND.
12	IS	I	Main Switch Current Sense	Connect to the drain of the main N-channel MosFET switch for R_DS-ON sensing or to a sense resistor installed in the source of the same device.
13	HSP	I	LED Current Sense Positive	Connect through a series resistor to LED current sense resistor (positive).
14	HSN	I	LED Current Sense Negative	Connect through a series resistor to LED current sense resistor (negative).
DAP (15)	DAP	GND	Thermal pad on bottom of IC	Connect to AGND and PGND.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Voltage	V_IN, nDIM	–0.3	76	V
	OVP, HSP, HSN	–0.3	76
	RCT	–0.3	3
	IS	–0.3	76
	IS		–2 for 100 ns
	V_CC	–0.3	8
	COMP, CSH	–0.3	6
	GATE	–0.3	V_CC
	GATE	–2.5 for 100 ns	V_CC+2.5 for 100 ns
	PGND	–0.3	0.3
	PGND	–2.5	2.5 for 100 ns
Continuous Current	V_IN, nDIM		–1	mA
	OVP, HSP, HSN		–100	µA
	RCT	–1	5	mA
	IS		–1	mA
	COMP, CSH	–200	200	µA
	GATE	–1	1	mA
Maximum Junction Temperature		Internally Limited
Maximum Lead Temperature (Reflow and Solder) ⁽³⁾			260	°C
Continuous Power Dissipation		Internally Limited
Storage Temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(3) Refer to http://www.ti.com/packaging for more detailed information and mounting techniques.

6.2 ESD Ratings

			VALUE	UNIT
LM3429 IN PWP PACKAGE
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V
LM3429-Q1 IN PWP PACKAGE
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽³⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per AEC Q100-011	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

	MIN	MAX	UNIT
Operating Junction Temperature Range	–40	125	°C
Input Voltage V_IN	4.5	75	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM3429-Q1	LM3429	UNIT
		PWP (HTSSOP)	PWP (HTSSOP)
		14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	47.8	47.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	26.5	26.5	°C/W
R_θJB	Junction-to-board thermal resistance	22.3	22.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.7	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter	22.1	22.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.3	3.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

MIN and MAX limits apply T_J = (−40°C to 125°C) unless specified otherwise. Unless otherwise stated the following condition applies: V_IN = 14 V.

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
STARTUP REGULATOR (V_CC)
V_CC-REG	V_CC Regulation	I_CC = 0 mA	6.3	6.9	7.35	V
I_CC-LIM	V_CC Current Limit	V_CC = 0V	20	27		mA
I_Q	Quiescent Current	Static		1.6	3	mA
V_CC-UVLO	V_CC UVLO Threshold	V_CC Increasing		4.17	4.5	V
V_CC-UVLO	V_CC UVLO Threshold	V_CC Decreasing	3.7	4.08
V_CC-HYS	V_CC UVLO Hysteresis			0.1
OVERVOLTAGE PROTECTION (OVP)
V_TH-OVP	OVP OVLO Threshold	OVP Increasing	1.18	1.24	1.28	V
I_HYS-OVP	OVP Hysteresis Source Current	OVP Active (high)	10	20	30	µA
ERROR AMPLIFIER
V_CSH	CSH Reference Voltage	With Respect to AGND	1.21	1.235	1.26	V
	Error Amplifier Input Bias Current	MIN, MAX: T_J = 25°C	–0.6	0	0.6	µA
	COMP Sink / Source Current		10	26	40	µA
	Transconductance			100		µA/V
	Linear Input Range	⁽³⁾		±125		mV
	Transconductance Bandwidth	-6dB Unloaded Response⁽³⁾, MIN: T_J = 25°C	0.5	1		MHz
OFF TIMER (RCT)
t_OFF-MIN	Minimum Off-time	RCT = 1V through 1 kΩ		35	75	ns
R_RCT	RCT Reset Pulldown Resistance			36	120	Ω
V_RCT	V_IN/25 Reference Voltage	V_IN = 14V	540	565	585	mV
PWM COMPARATOR
	COMP to PWM Offset		700	800	900	mV
CURRENT LIMIT (IS)
V_LIM	Current Limit Threshold		215	245	275	mV
	V_LIM Delay to Output			35	75	ns
t_ON-MIN	Leading Edge Blanking Time		75	250	450	ns
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
	Input Bias Current			10		µA
	Transconductance		20	119		mA/V
	Input Offset Current		–1.5	0	1.5	µA
	Input Offset Voltage		–7	0	7	mV
	Transconductance Bandwidth	I_CSH = 100 µA⁽³⁾, MIN: T_J = 25°C	250	500		kHz
GATE DRIVER (GATE)
R_SRC(GATE)	GATE Sourcing Resistance	GATE = High		2	6	Ω
R_SNK(GATE)	GATE Sinking Resistance	GATE = Low		1.3	4.5	Ω
UNDERVOLTAGE LOCKOUT and DIM INPUT (nDIM)
V_TH-nDIM	nDIM / UVLO Threshold		1.18	1.24	1.28	V
I_HYS-nDIM	nDIM Hysteresis Current		10	20	30	µA
THERMAL SHUTDOWN
T_SD	Thermal Shutdown Threshold	⁽³⁾		165		°C
T_HYS	Thermal Shutdown Hysteresis	⁽³⁾		25		°C

(1) All limits specified at room temperature (TYP) and at temperature extremes (MIN/MAX). All room temperature limits are 100% production tested. All limits at temperature extremes are specified through correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely norm.

(3) These electrical parameters are specified by design, and are not verified by test.

6.6 Typical Characteristics

T_A= 25°C and V_IN = 14 V unless otherwise specified. The measurements for Figure 1 and Figure 3 were made using the standard boost evaluation board from AN-1986 (SNVA404). The measurements for Figure 2, Figure 4, and Figure 5, Figure 6 were made using the standard buck-boost evaluation board from AN-1985 (SNVA403).