JAJSOT1J
December 2008 – June 2022
LM5088
,
LM5088-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings: LM5088
6.3
ESD Ratings: LM5088-Q1
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
High Voltage Low-Dropout Regulator
7.3.2
Line Undervoltage Detector
7.3.3
Oscillator and Sync Capability
7.3.4
Error Amplifier and PWM Comparator
7.3.5
Ramp Generator
7.3.6
Dropout Voltage Reduction
7.3.7
Frequency Dithering (LM5088-1 Only)
7.3.8
Cycle-by-Cycle Current Limit
7.3.9
Overload Protection Timer (LM5088-2 Only)
7.3.10
Soft Start
7.3.11
HG Output
7.3.12
Thermal Protection
7.4
Device Functional Modes
7.4.1
EN Pin Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Timing Resistor
8.2.2.2
Output Inductor
8.2.2.3
Current Sense Resistor
8.2.2.4
Ramp Capacitor
8.2.2.5
Output Capacitors
8.2.2.6
Input Capacitors
8.2.2.7
VCC Capacitor
8.2.2.8
Bootstrap Capacitor
8.2.2.9
Soft-Start Capacitor
8.2.2.10
Output Voltage Divider
8.2.2.11
UVLO Divider
8.2.2.12
Restart Capacitor (LM5008-2 Only)
8.2.2.13
MOSFET Selection
8.2.2.14
Diode Selection
8.2.2.15
Snubber Components Selection
8.2.2.16
Error Amplifier Compensation
8.2.3
Application Curves
9
Power Supply Recommendations
9.1
Thermal Considerations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
サポート・リソース
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PWP|16
MPDS371A
サーマルパッド・メカニカル・データ
PWP|16
PPTD288A
発注情報
jajsot1j_oa
jajsot1j_pm
6.3
ESD Ratings: LM5088-Q1
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±2000
V
Charged Device Model (CDM), per AEC Q100-011
All pins
±750
V
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.